| Electronic Components Datasheet Search |
|
CS8422 Datasheet(PDF) 59 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
CS8422 Datasheet(HTML) 59 Page - Cirrus Logic |
|
59 / 82 page ![]() DS692PP1 59 CS8422 CCRC - Channel Status Block Cyclic Redundancy Check bit. Updated on CS block boundaries, valid only in Pro mode. 0 - No error. 1 - Error. UNLOCK - Receiver lock status when sourced by incoming AES3-compatible data. Updated on CS block boundaries. 0 - Receiver locked. 1 - Receiver out of lock. V - Received AES3 Validity bit status. Updated on sub-frame boundaries. 0 - Data is valid and is normally linear coded PCM audio. 1 - Data is invalid, or may be valid compressed audio. CONF - Confidence bit. Updated on sub-frame boundaries. 0 - No error. 1 - Confidence error. The input data stream may be near error condition due to jitter degradation. BIP - Bi-phase error bit. Updated on sub-frame boundaries. 0 - No error. 1 - Bi-phase error. This indicates an error in the received bi-phase coding. PAR - Parity bit. Updated on sub-frame boundaries. 0 - No error. 1 - Parity error. 11.20 Interrupt Status (14h) For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register was last read. A “0” means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true. Status bits that are masked off in the associated mask register will always be “0” in this register. PCCH – PC burst preamble change. Indicates that the PC byte has changed from its previous value. If the IEC61937 bit in the Format Detect Status register goes high, it will cause a PCCH interrupt even if the PC byte hasn’t changed since the last time the IEC61937 bit went high. OSLIP - Serial audio output port data slip interrupt When the serial audio output port is in slave mode, and OLRCK is asynchronous to the port data source, this bit will go high every time a data sample is dropped or repeated. See “Serial Port Clock Operation” on page 25 for more information. 7 6 54321 0 PCCH OSLIP DETC CCH RERR QCH FCH SRC_UNLOCK |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |