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CS8422 Datasheet(PDF) 19 Page - Cirrus Logic |
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CS8422 Datasheet(HTML) 19 Page - Cirrus Logic |
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19 / 82 page ![]() DS692PP1 19 CS8422 9. Typical base band jitter in accordance with AES-12id-2006 section 3.4.2. Measurements are Time In- terval Error (TIE) taken with 3rd order 100 Hz to 40 kHz band-pass filter. Measured with Sample Rate = 48 kHz. 10. OLRCK must remain high for at least 1 OSCLK period and at most 255 OSCLK periods in TDM Mode. 11. In TDM formatted master mode, the OSCLK frequency is fixed at 256*OLRCK. t ds OLRCK (input) t dh t sckh t sckl t fsh t fss OSCLK (input) TDM_IN (input) SDOUT (output) MSB t dpd MSB-1 MSB MSB-1 t lrckh t ds MSB t dh t dpd MSB-1 I/OLRCK (input) I/OSCLK (input) SDIN (input) SDOUT (output) MSB MSB-1 t sckh t sckl t lcks t lckd Figure 1. Non-TDM Slave Mode Timing Figure 2. TDM Slave Mode Timing tds OLRCK (output) tdh tdpd tfsm OSCLK (output) TDM_IN (input) SDOUT (output) MSB MSB-1 MSB MSB-1 t ds MSB t dh t dpd MSB-1 t lcks I/OLRCK (output) I/OSCLK (output) SDIN (input) SDOUT (output) MSB MSB-1 Figure 3. Non-TDM Master Mode Timing Figure 4. TDM Master Mode Timing |
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