Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

CS8422 Datasheet(PDF) 18 Page - Cirrus Logic

Part # CS8422
Description  24-bit, 192 kHz, Asynchronous Sample Rate Converter with
PDF  82 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS8422 Datasheet(HTML) 18 Page - Cirrus Logic

Back Button CS8422 Datasheet HTML 14Page - Cirrus Logic CS8422 Datasheet HTML 15Page - Cirrus Logic CS8422 Datasheet HTML 16Page - Cirrus Logic CS8422 Datasheet HTML 17Page - Cirrus Logic CS8422 Datasheet HTML 18Page - Cirrus Logic CS8422 Datasheet HTML 19Page - Cirrus Logic CS8422 Datasheet HTML 20Page - Cirrus Logic CS8422 Datasheet HTML 21Page - Cirrus Logic CS8422 Datasheet HTML 22Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 18 / 82 page
background image
18
DS692PP1
CS8422
Notes:
7.
After powering up the CS8422, RST should be held low until the power supplies and clocks are settled.
8.
If ISCLK is selected as the clock source for the PLL, then the Sample Rate = ISCLK/64.
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge
tds
2.2
-
-
ns
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge
tdh
5.5
-
-
ns
TDM Mode OSCLK Frequency (Note 11)
-
-
49.152
MHz
TDM Mode OSCLK Falling Edge to OLRCK Edge
tfsm
--
4.2
ns
VL = 1.8 V, 2.5 V
RMCK Output Frequency
--
31
MHz
MCLK_OUT Frequency
--
31
MHz
Slave Mode
ISCLK Frequency
-
-
49.152
MHz
ISCLK High Time
tsckh
9.2
-
-
ns
ISCLK Low Time
tsckl
9.2
-
-
ns
OSCLK Frequency
--
15.7
MHz
OSCLK High Time
tsckh
28.7
-
-
ns
OSCLK Low Time
tsckl
28.7
-
-
ns
I/OLRCK Edge to I/OSCLK Rising Edge
tlcks
7.4
-
-
ns
I/OSCLK Rising Edge to I/OLRCK Edge
tlckd
6.2
-
-
ns
OSCLK Falling Edge/OLRCK Edge to SDOUT Output
Valid
tdpd
--
25.6
ns
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge
tds
4.7
-
-
ns
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge
tdh
7.3
-
-
ns
TDM Mode OLRCK High Time (Note 10)
tlrckh
20
-
-
ns
TDM Mode OLRCK Rising Edge to OSCLK Rising Edge
tfss
7.0
-
-
ns
TDM Mode OSCLK Rising Edge to OLRCK Falling Edge
tfsh
6.2
-
-
ns
Master Mode
I/OSCLK Frequency (non-TDM Mode)
48*Fsi/o
-
128*Fsi/o
MHz
I/OLRCK Duty Cycle
45
-
55
%
I/OSCLK Duty Cycle
45
-
55
%
I/OSCLK Falling Edge to I/OLRCK Edge
tlcks
--
5.7
ns
OSCLK Falling Edge to SDOUT Output Valid
tdpd
--
5.4
ns
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge
tds
4.7
-
-
ns
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge
tdh
7.3
-
-
ns
TDM Mode OSCLK Frequency (Note 11)
--
31
MHz
TDM Mode OSCLK Falling Edge to OLRCK Edge
tfsm
--
5.7
ns
Parameter
Symbol
Min
Typ
Max
Units



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com