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CS8422 Datasheet(PDF) 20 Page - Cirrus Logic

Part # CS8422
Description  24-bit, 192 kHz, Asynchronous Sample Rate Converter with
PDF  82 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS8422 Datasheet(HTML) 20 Page - Cirrus Logic

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20
DS692PP1
CS8422
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF.
Notes:
12. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. CDOUT should not be sampled during this time.
15. For fsck < 1 MHz.
Parameter
Symbol
Min
Max
Unit
CCLK Clock Frequency
fsck
06.0
MHz
RST Rising Edge to CS Falling
tsrs
500
-
µs
CCLK Edge to CS Falling (Note 12)
tspi
500
-
ns
CS High Time Between Transmissions
tcsh
1.0
-
µs
CS Falling to CCLK Edge
tcss
20
-
ns
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
ns
CCLK Rising to DATA Hold Time (Note 13)
tdh
15
-
ns
CCLK Falling to CDOUT Valid (Note 14)
tscdov
-100
ns
Time from CS Rising to CDOUT High-Z
tcscdo
-100
ns
CDOUT Rise Time
tr1
-25
ns
CDOUT Fall Time
tf1
-25
ns
CCLK and CDIN Rise Time (Note 15)
tr2
-100
ns
CCLK and CDIN Fall Time (Note 15)
tf2
-100
ns
t r2
t f2
t dsu tdh
t sch
t scl
CS
CCLK
CDIN
tcss
t csh
t spi
t srs
RST
CDOUT
t scdov
t scdov
t cscdo
Hi-Impedance
Figure 5. SPI Mode Timing



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