7

6399A–DRMSD–13-Oct-08

ATSAM2553

4.

Pin Description

5VT indicates a 5 volt tolerant Input or I/O pin.

4.1

Pins by Function

Power supply decoupling note: like all high speed HCMOS ICs, proper decoupling is mandatory

for reliable operation and RFI reduction. The recommended decoupling is 100 nF at each corner

of the IC with an additional 10 µFT bulk capacitor close to the X1, X2 pins.

Table 4-1.

Power Supply

Pin Name

Pin#

Type

Function

GND

1, 14, 33, 48,

65, 85, 97, 98,

116

PWR

DIGITAL GROUND All pins should be connected to a

ground plane

AGND

16

PWR

ANALOG GROUND for the ADC. Should be connected to

a clean analog ground.

VD33

18, 32, 40, 49,

64, 84, 96,

115, 128

PWR

POWER SUPPLY, 3.3V ± 10%

All pins should be connected to a VD33 plane

VD18

100

PWR

Power for the internal PLL, +1.8V nominal (1.8V ± 10%).

These pins can be connected to the output of the regulator

OUTVC18 (pin 41).

A 100 nF decoupling capacitor should be connected

between this pin and PLL ground (pin98)

VA33

17

PWR

Analog power for the ADC, +3.3V nominal (3,3V ± 10%).

Table 4-2.

Serial MIDI

Pin Name

Pin#

Type

Function

MIDI-IN

127

IN 5VT

Serial MIDI IN. This pin has a built-in pull up

MIDI-OUT

126

OUT

Serial MIDI OUT.

Table 4-3.

External PCM ROM/RAM/IO

Pin Name

Pin#

Type

Function

WA0-WA24

42-47,50-

55,66-78

OUT

External memory I/O Address, up to 32 Mega x 16 for

direct ROM/RAM connection.

WD0-WD15

21-31,34-38

I/O 5VT

External memory I/O data. Data is read (input) when RD is

low, written (output) when WR is low.

WOE

94

OUT

External ROM/RAM peripherals output enable.

WWE

95

OUT

External RAM peripherals write enable.

WCS0 -WCS1 92,93

OUT

Programmable chip selects. Can be configured to handle

several ROMs or mixed RAM/ROM/Flash.

XIO

20

OUT

External peripheral chip select. XIO maps its peripheral

into 4k bytes address space for optional further decoding.