15

6399A–DRMSD–13-Oct-08

ATSAM2553

8.

Timings

All timings conditions: VD33=3.3V, VD18=1.8V, TA=25°C, all outputs except X2, have load

capacitance = 30 pF.

All timings refer to tck, which is the internal master clock period.

The internal master clock frequency is 4 times the frequency at pin X1. Therefore tck=txtal/4.

The sampling rate is given by 1/(tck*1024). The maximum crystal frequency/clock frequency at

X1 is 12.288 MHz (48 KHz sampling rate).

8.1

Crystal Frequency Selection Considerations

There is a trade-off between the crystal frequency and the support of widely available external

ROM/Flash components. Table 8-1 allows to select the best fit for a given application;

Using 12.288 MHz crystal frequency allows to use widely available ROM/Flash with 90 ns

access time, while providing state of the art 48 kHz sampling rate.

Table 8-1.

Crystal Frequency Selection Chart

Sample Rate (kHz)

Xtal (MHz)

tck (ns)

ROM tA (ns)

Comments

48

12.288

20.35

92

Recommended for current designs.

44.1

11.2896

22.14

101

37.5

9.60

26.04

120

31.25

8.00

31.25

146