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ATSAM2553 Datasheet(PDF) 17 Page - ATMEL Corporation |
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ATSAM2553 Datasheet(HTML) 17 Page - ATMEL Corporation |
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17 / 29 page  17 6399A–DRMSD–13-Oct-08 ATSAM2553 8.3 External ROM/Flash, RAM, I/O Read Timing Figure 8-2. External ROM/Flash, RAM, I/O Read Timing WCS0/ WCS1/ XIO/ WA0- WA24 WOE/ WD0- WD15 tCSOE tRC tPOE tOE tDF tACE Table 8-3. Timing Parameters Symbol Parameter Min Typ Max Unit tRC Read cycle time 5*tck - 6*tck ns tCSOE Chip select low / address valid to WOE/ low 2*tck-5 - 3*tck+5 ns tPOE Output enable pulse width - 3*tck - ns tACE Chip select/address access time 5*tck-5 - - ns tOE Output enable access time 3*tck-5 - - ns tDF Chip select or WOE/ high to input data Hi-Z 0 - 2*tck-5 ns |
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