| Electronic Components Datasheet Search |
|
3507 Datasheet(PDF) 19 Page - Linear Technology |
|
|
|||||||||||||||||||||||||||||
3507 Datasheet(HTML) 19 Page - Linear Technology |
|
19 / 28 page ![]() LT3507 19 3507f the TRK/SS2 voltage is substantially higher than 0.8V at steady state and effectively turns off D1. D2 and D3 will therefore conduct the same current and offer tight matching between VFB2 and the internal precision 0.8V reference. In the ratiometric mode with R6 = R2, TRK/SS2 equals 0.8V at steady state. D1 will divert part of the bias current and make VFB2 slightly lower than 0.8V. Although this error is minimized by the exponential I-V characteristic of the diodes, it does impose a finite amount of output voltage deviation. Further, when channel 1’s output experiences dynamic excursions (under load transient, for example), channel 2 will be affected as well. Setting R6 to a value that pushes the TRK/SS2 voltage to 1V at steady state will eliminate these problems while providing near ratiometric tracking. The example shows channel 2 tracking channel 1, however any channel may be set up to track any other channel. If a capacitor is tied from the TRK/SS pin to ground, then the internal pull-up current will generate a voltage ramp on this pin. This results in a ramp at the output, limiting the inductor current and therefore input current during start-up. A good value for the soft-start capacitor is COUT/10,000, where COUT is the value of the output capacitor. MULTIPLE INPUT SUPPLIES VIN1, VIN2 and VIN3 are independent and can be powered with different voltages provided VIN1 is present when VIN2 or VIN3 is present. Each supply must be bypassed as close to the VIN pins as possible. For applications requiring large inductors due to high VIN to VOUT ratios, a 2-stage step-down approach may reduce inductor size by allowing an increase in frequency. A dual step-down application steps down the input voltage (VIN1) to the highest output voltage, then uses that voltage to power the other outputs (VIN2 and VIN3). VOUT1 must be able to provide enough current for its output plus the input current at VIN2 and VIN3 when VOUT2 and VOUT3 are at maximum load. The Typical Applications section shows a 36V to 15V, 1.8V and 1.2V 2-stage converter using this approach. For applications with multiple voltages, the LT3507 can accommodate input voltages as low as 3V on VIN2 and APPLICATIONS INFORMATION VIN3. This can be useful in applications regulating outputs from a PCI Express bus, where the 12V input is power limited and the 3.3V input has power available to drive other outputs. In this case, tie the 12V input to VIN1 and the 3.3V input to VIN2 and VIN3. LOW DROPOUT REGULATOR The low dropout regulator comprises an error amp, loop compensation and a base drive amp. It uses the same 0.8V reference as the switching regulators. It requires an external NPN pass transistor and 2.2μF of output capaci- tance for stability. The dropout characteristics will be determined by the pass transistor. The collector-emitter saturation characteristics will limit the dropout voltage. Table 4 lists some suitable NPN transistors with their saturation specifications. The base drive voltage has a maximum voltage of 5V. This will limit the maximum output of the regulator to 5V – VBESAT where VBESAT is the base-emitter saturation voltage of the pass transistor. Table 4. NPN Pass Transistors and Saturation Characteristics PART NUMBER VCESAT VBESAT IC (mA) IB (mA) On Semiconductor NSS30071 0.25 0.85 500 5 NSS30101 0.2 0.85 1000 10 Fairchild KSC3265 0.4 500 20 The LDO is always on when any of the switcher channels is on. The LDO may be shut down if it is unused by pull- ing the FB4 pin up with a 30μA current source. The FB4 pin will clamp at about 1.25V and the LDO will shut off reducing power consumption. This pull-up can be sourced from one of the LT3507 outputs provided that channel is always on when the other channels are on. The output stage of the LDO will drive the NPN base from the BIAS voltage if it is at least 0.8V above the LDO DRIVE voltage. FB Resistor Network The output voltage of the LDO regulator is programmed with a resistor divider (Refer to Block Diagram) between the |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |