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LT5560

5560f

APPLICATIO S I FOR ATIO

Signal Output Port

A simpliﬁed schematic of the output circuit is shown in

Figure 9. The output pins, OUT+ and OUT–, are internally

connected to the collectors of the mixer transistors. These

pins must be biased at the supply voltage, which can be

applied through a transformer center-tap, impedance

matching inductors, RF chokes, or pull-up resistors. With

external resistor R1 = 3Ω (Figures 1 to 3), each OUT pin

draws about 4.5mA of supply current. For optimum per-

formance, these differential outputs should be combined

externally through a transformer or balun.

An equivalent small-signal model for the output is shown

in Figure 10. The output impedance can be modeled as

a 1.2kΩ resistor in parallel with a 0.7pF capacitor. For

low frequency applications, the 0.7nH series bond-wire

inductances can be ignored.

The external components, C2, L3 and L4, form a lowpass

impedance transformation network to match the mixer

output impedance to the input impedance of transformer

T2. The values for these components can be estimated

Figure 9. Output Port Schematic

Figure 10. Output Port Small-Signal Model

with External Matching

OUT+

OUT–

0.7pF

LT5560

1.2k

VCC

5560 F09

using the impedance parameters listed in Table 6 along

with similar equations as used for the input matching net-

work. As an example, at an output frequency of 140MHz

and RL = 200Ω (using a 4:1 transformer for T2),

1082

200

541

=−

() =

12 10

== 515Ω

221

ω •

C2 = C – CINT = 1.51pF

XL = RL • Q = 420Ω

239

OUT

LT5560

C10

0.7nH

VCC

5560 F10

OUT+

OUT–

CINT

0.7pF

RINT

1.2k

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