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LTC4444 Datasheet(PDF) 3 Page - Linear Technology

Part # LTC4444
Description  High Voltage Synchronous N-Channel MOSFET Driver
PDF  12 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC4444 Datasheet(HTML) 3 Page - Linear Technology

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LTC4444
3
4444f
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC4444E is guaranteed to meet specifications from
0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC4444I is guaranteed over the full
–40°C to 85°C operating temperature range.
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = VBOOST = 12V, VTS = GND = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
High Side Gate Driver Output (TG)
VOH(TG)
TG High Output Voltage
ITG = –10mA, VOH(TG) = VBOOST – VTG
0.7
V
VOL(TG)
TG Low Output Voltage
ITG = 100mA, VOL(TG) = VTG –VTS
●
120
220
mV
IPU(TG)
TG Peak Pull-Up Current
●
1.7
2.5
A
RDS(TG)
TG Pull-Down Resistance
●
1.2
2.2
Ω
Low Side Gate Driver Output (BG)
VOH(BG)
BG High Output Voltage
IBG = –10mA, VOH(BG) = VCC – VBG
0.7
V
VOL(BG)
BG Low Output Voltage
IBG = 100mA
●
55
110
mV
IPU(BG)
BG Peak Pull-Up Current
●
23
A
RDS(BG)
BG Pull-Down Resistance
●
0.55
1.1
Ω
Switching Time (BINP (TINP) is Tied to Ground While TINP (BINP) is Switching. Refer to Timing Diagram)
tPLH(TG)
TG Low-High Propagation Delay
●
25
45
ns
tPHL(TG)
TG High-Low Propagation Delay
●
22
40
ns
tPLH(BG)
BG Low-High Propagation Delay
●
19
35
ns
tPHL(BG)
BG High-Low Propagation Delay
●
14
30
ns
tr(TG)
TG Output Rise Time
10% – 90%, CL = 1nF
10% – 90%, CL = 10nF
8
80
ns
ns
tf(TG)
TG Output Fall Time
10% – 90%, CL = 1nF
10% – 90%, CL = 10nF
5
50
ns
ns
tr(BG)
BG Output Rise Time
10% – 90%, CL = 1nF
10% – 90%, CL = 10nF
6
60
ns
ns
tf(BG)
BG Output Fall Time
10% – 90%, CL = 1nF
10% – 90%, CL = 10nF
3
30
ns
ns
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
TJ = TA + (PD • θJA°C/W)
Note 4: Failure to solder the exposed back side of the MS8E package to the
PC board will result in a thermal resistance much higher than 40°C/W.



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