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LTM4603/LTM4603-1

4603f

to the rising edge of the external clock. The frequency

range is ±30% around the operating frequency of 1MHz.

A pulse detection circuit is used to detect a clock on the

PLLIN pin to turn on the phase lock loop. The pulse width

of the clock has to be at least 400ns and 2V in amplitude.

During the start-up of the regulator, the phase-lock loop

function is disabled.

INTVCC and DRVCC Connection

An internal low dropout regulator produces an internal

5V supply that powers the control circuitry and DRVCC

for driving the internal power MOSFETs. Therefore, if

the system does not have a 5V power rail, the LTM4603

can be directly powered by Vin. The gate driver current

through the LDO is about 20mA. The internal LDO power

dissipation can be calculated as:

PLDO_LOSS = 20mA • (VIN – 5V)

The LTM4603 also provides the external gate driver volt-

age pin DRVCC. If there is a 5V rail in the system, it is

recommended to connect DRVCC pin to the external 5V

rail. This is especially true for higher input voltages. Do

not apply more than 6V to the DRVCC pin. A 5V output can

be used to power the DRVCC pin with an external circuit

as shown in Figure 16.

Parallel Operation of the Module

The LTM4603 device is an inherently current mode con-

trolled device. Parallel modules will have very good current

sharing. This will balance the thermals on the design. The

voltage feedback equation changes with the variable

η as

modules are paralleled:

OUT

60 4

η is the number of paralleled modules.

Thermal Considerations and Output Current Derating

The power loss curves in Figures 7 and 8 can be used

in coordination with the load current derating curves in

Figures 9 to 12, and Figures 13 to 14 for calculating an

approximate

θJA for the module with various heat sinking

methods. Thermal models are derived from several tem-

perature measurements at the bench and thermal modeling

analysis. Thermal Application Note 103 provides a detailed

explanation of the analysis for the thermal models and the

derating curves. Tables 3 and 4 provide a summary of the

equivalent

θJA for the noted conditions. These equivalent

θJA parameters are correlated to the measured values,

and are improved with air ﬂow. The case temperature is

maintained at 100°C or below for the derating curves.

This allows for 4W maximum power dissipation in the

total module with top and bottom heatsinking, and 2W

power dissipation through the top of the module with an

approximate

θJC between 6°C/W to 9°C/W. This equates

to a total of 124°C at the junction of the device.

APPLICATIO S I FOR ATIO

Figure 7. 1.5V Power Loss

Figure 8. 3.3V Power Loss

Figure 9. No Heat Sink

OUTPUT CURRENT (A)

2.0

2.5

3.5

4603 F07

1.5

1.0

0.5

3.0

20V LOSS

12V LOSS

5V LOSS

OUTPUT CURRENT (A)

2.0

2.5

3.5

4603 F08

1.5

1.0

0.5

3.0

20V LOSS

12V LOSS

AMBIENT TEMPERATURE (

°C)

4603 F09

5VIN, 1.5VOUT, 0LFM

5VIN, 1.5VOUT, 200LFM

5VIN, 1.5VOUT, 400LFM

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