BQ2018TS datasheet(5/21 Pages) TI

5 / 21 page

During charge, the CCR and the Charge Time Counter

(CTC) are active. If VSR1 is greater than VSR2, indicating

a charge, the CCR counts at a rate equivalent to 12.5

µV

every hour, and the CTC counts at a rate of 1

count/0.8789 seconds. For example, a +100mV signal pro-

duces 8000 CCR counts and 4096 CTC counts each hour.

The amount of charge added to the battery can easily be

calculated.

The DTC and the CTC are 16-bit registers, and roll over

beyond ffffh. If a rollover occurs, the corresponding bit in

the MODE/WOE register is set, and the counter will sub-

sequently increment at 1/256 of the normal rate (16

counts/hr.).

Whenever the signal between SR1 and SR2 is above the

Wakeup Output Enable (WOE) threshold and the HDQ

pin is high, the bq2018 is in its full operating state. In

this state, the DCR, CCR, DTC, CTC, and SCR are fully

operational, and the WAKE output is low. During this

mode, the internal RAM registers of the bq2018 may be

accessed over the HDQ pin, as described in the section

“Communicating With the 2018.”

If the signal between SR1 and SR2 is below the WOE

threshold (refer to the WAKE section for details) and

HDQ remains low for greater than 10 seconds, the

bq2018 enters a sleep mode where all register counting is

suspended. The bq2018 remains in this mode until HDQ

returns high.

For self-discharge calculation, the self-discharge count

every hour at a nominal 25°C and doubles approximately

every 10°C up to 60°C. The SCR count rate is halved

every 10

°C below 25°C down to 0°C. The value in SCR is

useful in determining an estimation of the battery self-

discharge based on capacity and storage temperature

conditions.

The bq2018 may be programmed to measure the voltage

offset between SR1 and SR2 during pack assembly or at

any time by invoking the Calibration mode. The Offset

bit 2’s complement value stored in the OFR is scaled to

the same units as the DCR and CCR, representing the

amount of positive or negative offset in the bq2018. The

maximum offset for the bq2018 is specified as

± 500µV.

Care should be taken to ensure proper PCB layout. Us-

ing OFR, the system host can cancel most of the effects of

bq2018 offset for greater resolution and accuracy.

Figure 3 shows the bq2018 register address map. The

bq2018 uses the upper 13 locations.

The remaining

memory can store user-specific information such as

chemistry, serial number, and manufacturing date.

WAKE Output

This output is used to inform the system that the voltage

difference between SR1 and SR2 is above or below the

Wake Output Enable (WOE) threshold programmed in

the MODE/WOE register. When the voltage difference

between SR1 and SR2 is below VWOE, the WAKE output

goes into High Z and remains in this state until the dis-

charge or charge current increases above the specified

value. The MODE/WOE resets to 0eh after a power-on

reset. VWOE is set by dividing 3.84mV by a value be-

tween 1 and 7 (1–7h) according to Table 3.

bq2018

User

RAM

Discharge count high byte

Discharge count low byte

Charge count high byte

Charge count low byte

Self-discharge high byte

Self-discharge low byte

Discharge time high byte

Discharge time low byte

Charge time high byte

Charge time low byte

Mode/wake output enable

Temperature/clear

Offset register

FG201801.eps

Figure 3. Address Map

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