BQ2018TS datasheet(9/21 Pages) TI

9 / 21 page

of the discharge, and are incremented whenever VSR1 <

VSR2. These registers continue to count beyond ffffh, so

proper register maintenance should be done by the host

system. The TMP/CLR register is used to force the reset

of both the DCRH and DCRL to zero.

Charge Count Registers (CCRH/CCRL)

The CCRH high-byte register (address = 7dh) and the

CCRL low-byte register (address = 7ch) contain the count

of the charge, and are incremented whenever VSR1 >

VSR2. These registers continue to count beyond ffffh, so

proper register maintenance should be done by the host

system. The TMP/CLR register is used to force the reset

of both the CCRH and CCRL to zero.

Self-discharge Count Registers

(SCRH/SCRL)

The SCRH high-byte register (address = 7bh) and the

SCRL low-byte register (address = 7ah) contain the self-

discharge count.

This register is continually updated

whenever the bq2018 is in its normal operating mode.

The counts in these registers are incremented based on

time and temperature. The SCR counts at a rate of 1

count per hour at 20–30°C and doubles every 10°C to

greater than 60°C (16 counts/hour). The count will half

every 10°C below 20–30°C to less than 0°C (1 count/8

hours). These registers continue to count beyond ffffh, so

proper register maintenance should be done by the host

system. The TMP/CLR register is used to force the reset

of both the SCRH and SCRL to zero.

Discharge Time Count Registers

(DTCH/DTCL)

The DTCH high-byte register (address = 79h) and the

DTCL low-byte register (address = 78h) are used to deter-

mine the length of time the VSR1 <VSR2 indicating a dis-

charge. The counts in these registers are incremented at

a rate of 4096 counts per hour. If the DTCH/DTCL regis-

ter continues to count beyond ffffh, the STD bit is set in

the MODE/WOE register indicating a rollover. Once set,

DTCH and DTCL increment at a rate of 16 counts per

hour. Note: If a second rollover occurs, STD is

cleared. Access to the bq2018 should be timed to

clear DTCH/DTCL more often than every 170 days.

The TMP/CLR register is used to force the reset of both

the DTCH and DTCL to zero.

Charge Time Count Registers (CTCH/CTCL)

The CTCH high-byte register (address = 77h) and the

CTCL low-byte register (address = 76h) are used to deter-

mine the length of time the VSR1 >VSR2 indicating a

charge. The counts in these registers are incremented at

a rate of 4096 counts per hour. If the CTCH/CTCL regis-

ters continue to count beyond ffffh, the STC bit is set in

the MODE/WOE register indicating a rollover. Once set,

DTCH and DTCL increment at a rate of 16 counts per

hour.

Note: If a second rollover occurs, STC is

cleared. Access to the bq2018 should be timed to

clear CTCH/CTCL more often than every 170 days.

The TMP/CLR register is used to force the reset of both

the CTCH and CTCL to zero.

Mode/Wake-up Enable Register

The Mode/WOE register (address = 75h) contains the

calibration, wakeup enable information, and the STC and

STD bits as described below.

The Override DQ(OVRDQ) bit (bit 7) is used to override

the requirement for HDQ to be low prior to initiating VOS

calibration. This bit is normally set to zero. If OVRDQ is

written to one, the bq2018 begins offset calibration when

|VSR|<VWOE where HDQ = Don’t care.

The OVRDQ location is

MODE/WOE Bits

OVRDQ

Where OVRDQ is

HDQ = 0 and |VSR|<VWOE for VOS calibra-

tion to begin

HDQ = Don’t care and |VSR|<VWOE for VOS

calibration to begin

Note: The OVRDQ bit should only be used in con-

junction with a calibration cycle. Normal opera-

tion of the bq2018 cannot be guaranteed when

this bit is set. After a valid calibration cycle, bit 7

is reset to zero.

The calibration (CAL) bit 6 is used to enable the bq2018

offset calibration test. Setting this bit to 1 enables a VOS

calibration whenever HDQ is low (default), and |VSRO|<

VWOE. This bit is cleared to 0 by the bq2018 whenever a

valid VOS calibration is completed, and the OFR register

is updated with the new calculated offset. The bit re-

mains 1 if the offset calibration was not completed.

The CAL location is

MODE/WOE Bits

-CAL

Where CAL is

Valid offset calibration

Offset calibration pending

bq2018

BQ2018TS Datasheet(PDF) 9 Page - Texas Instruments

BQ2018TS Datasheet(HTML) 9 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

Datasheet Download

Link URL