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BQ2018TS Datasheet(PDF) 11 Page - Texas Instruments |
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BQ2018TS Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 21 page  11 The Clear bit locations are TMP/CLR Bits 76 5 4 3 2 1 0 - - - CTC DTC SCR CCR DCR Where: CTC bit (bit 4) resets both the CTCH and CTCL registers and the STC bit to 0. The DTC bit (bit 3) resets both the DTCH and DTCL registers and the STD bit to 0. The SCR bit (bit 2) resets both the SCRH and SCRL reg- isters to 0. The CCR bit (bit 1) resets both the CCRH and CCRL registers to 0. The DCR bit (bit 0) resets both the DCRH and DCRL registers to 0. Offset Register (OFR) The OFR register (address = 73h) is used to store the cal- culated VOS of the bq2018. The OFR value can be used to cancel the voltage offset between VSR1 and VSR2. The up/down offset counter is centered at zero. The actual off- set is an 8-bit two’s complement value located in OFR. The OFR locations are OFR Bits 7 6 54 32 1 0 OFR7 OFR6 OFR5 OFR4 OFR3 OFR2 OFR1 OFR0 Where OFR7 is 1 Discharge 0 Charge bq2018 |
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