BQ2018TS datasheet(10/21 Pages) TI

10 / 21 page

The slow time charge (STC) and slow time discharge

(STD) flags indicate if the CTC or DTC registers have

rolled over beyond ffffh. STC set to 1 indicates a CTC

rollover; STD set to 1 indicates a DTC rollover.

The STC and STD locations are

MODE/WOE Bits

STC

STD

Where STC/STD is

No rollover

Rollover occurred in the corresponding

CTC/DTC register.

The Wake Up Output Enable (WOE) bits (bits 3–1) are

used to set the Wake-Up Enable signal level. Whenever

|VSRO |<VWOE, the WAKE output is in High Z. If

|VSRO| is greater than VWOE, WAKE transitions low. On

bq2018 initialization (power-on reset) these bits are set to

1. Setting all of these bits to zero is not valid. Refer to

Table 3 for the various WOE values.

The WOE 3–1 locations are

MODE/WOE Bits

WOE3

WOE2

WOE1

Where WOE3–1 is determined by dividing 3.84mV by the

value in WOE.

Bit 0 is reserved and must remain 0.

Temperature and Clear Register

The TMP/CLR register (address = 74h) is used to give the

present temperature step between < 0°C to > 60°C and

clear the various count registers.

The values of the

TMP0–TMP2 (bits 5–7) denote the current temperature

step sense by the bq2018 as outlined in Table 4. The

bq2018 temperature sense is trimmed to ±

2°C typical

(± 4°C maximum).

The TMP2–0 locations are

TMP/CLR Bits

TMP2 TMP1 TMP0

Where TMP2–0 is the temperature step sensed by this

bq2018.

The Clear bits (Bits 0–4) are used to reset the various

bq2018 counters and STC and STD bits to zero. Writing

the bits to 1 resets the corresponding register to 0. The

clear bit resets to 0 indicating a successful register reset.

Each clear bit is independent, so it is possible to clear the

DCRH/DCRL registers without affecting the values in

any other bq2018 register. The high-byte and low-byte

registers are both cleared when the corresponding bit is

written to 1 per the figure below.

bq2018

Send Host to bq-HDQ

CDMR

Send Host to bq-HDQ or

Receive from bq-HDQ

Data

Address

Break

LSB

Bit0

R/W

MSB

Bit7

TD201807.eps

Start-bit

Address-Bit/

Data-Bit

Stop-Bit

tRR

tRSPS

Figure 5. Communications Frame Example

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