CDC582

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

WITH DIFFERENTIAL LVPECL CLOCK INPUTS

SCAS446B – JULY 1994 – REVISED FEBRUARY 1996

2

POST OFFICE BOX 655303

description (continued)

The Y outputs can be configured to switch in phase and at the same frequency as differential clock inputs

(CLKIN and CLKIN). Select (SEL1, SEL0) inputs configure up to nine Y outputs, in banks of three, to operate

at one-half or double the differential clock input frequency, depending upon the feedback configuration

(see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty cycle at the input

clocks.

Output-enable (OE) is provided for output control. When OE is high, the outputs are in the low state. When OE

is low, the outputs are active. CLR is negative-edge triggered and can be used to reset the outputs operating

at half frequency. TEST is used for factory testing of the device and can be used to bypass the PLL. TEST should

be strapped to GND for normal operation.

Unlike many products containing a PLL, the CDC582 does not require external RC networks. The loop filter for

the PLL is included on chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC582 requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required following power up and application

of a fixed-frequency, fixed-phase signal at CLKIN and CLKIN, as well as following any changes to the PLL

reference or feedback signal. Such changes occur upon change of SEL1 and SEL0, enabling the PLL via TEST,

and upon enable of all outputs via OE.

The CDC582 is characterized for operation from 0

°C to 70°C.

detailed description of output configurations

The voltage-controlled oscillator (VCO) used in the CDC582 has a frequency range of 100 MHz to 200 MHz,

twice the operating frequency range of the CDC582 outputs. The output of the VCO is divided by 2 and by 4

to provide reference frequencies with a 50% duty cycle of one-half and one-fourth the VCO frequency. SEL0

and SEL1 determine which of the two signals are buffered to each bank of device outputs.

One device output must be externally wired to FBIN to complete the PLL. The VCO operates such that the

frequency of this output matches that of the CLKIN/CLKIN signals. In the case that a VCO/2 output is wired to

FBIN, the VCO must operate at twice the CLKIN/CLKIN frequency, resulting in device outputs that operate at

the same or one-half the CLKIN/CLKIN frequency. If a VCO/4 output is wired to FBIN, the device outputs operate

at the same or twice the CLKIN/CLKIN frequency.

output configuration A

Output configuration A is valid when any output configured as a 1

× frequency output in Table 1 is fed back to

FBIN. The frequency range for the differential clock input is 50 MHz to 100 MHz when using output configuration

A. Outputs configured as 1/2

× outputs operate at half the input clock frequency, while outputs configured as 1×

outputs operate at the same frequency as the differential clock input.

Table 1. Output Configuration A

INPUTS

OUTPUTS

SEL1

SEL0

1/2

×

FREQUENCY

1

×

FREQUENCY

L

L

None

All

L

H

1Yn

2Yn, 3Yn, 4Yn

H

L

1Yn, 2Yn

3Yn, 4Yn

H

H

1Yn, 2Yn, 3Yn

4Yn

NOTE: n = 1, 2, 3