CDC582

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

WITH DIFFERENTIAL LVPECL CLOCK INPUTS

SCAS446B – JULY 1994 – REVISED FEBRUARY 1996

3

POST OFFICE BOX 655303

output configuration B

Output configuration B is valid when any output configured as a 1

× frequency output in Table 2 is fed back to

FBIN. The frequency range for the differential clock inputs is 25 MHz to 50 MHz when using output configuration

B. Outputs configured as 1

× outputs operate at the input clock frequency, while outputs configured as 2× outputs

operate at double the frequency of the differential clock inputs.

Table 2. Output Configuration B

INPUTS

OUTPUTS

SEL1

SEL0

1

×

FREQUENCY

2

×

FREQUENCY

L

L

All

None

L

H

1Yn

2Yn, 3Yn, 4Yn

H

L

1Yn, 2Yn

3Yn, 4Yn

H

H

1Yn, 2Yn, 3Yn

4Yn

NOTE: n = 1, 2, 3