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PCI2250 Datasheet(PDF) 43 Page - Texas Instruments |
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PCI2250 Datasheet(HTML) 43 Page - Texas Instruments |
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43 / 85 page  4–9 4.17 I/O Base Register The I/O base register is used in decoding I/O addresses to pass through the bridge. The bridge supports 32-bit I/O addressing; thus, bits 3–0 are read-only and default to 0001b. The upper four bits are writable and correspond to address bits AD15–AD12. The lower 12 address bits of the I/O base address are considered 0. Thus, the bottom of the defined I/O address range is aligned on a 4K-byte boundary. The upper 16 address bits of the 32-bit I/O base address corresponds to the contents of the I/O base upper 16 bits register (offset 30h, see Section 4.26). Bit 7 6 5 4 3 2 1 0 Name I/O base Type R/W R/W R/W R/W R R R R Default 0 0 0 0 0 0 0 1 Register: I/O base Type: Read-only, read/write Offset: 1Ch Default: 01h 4.18 I/O Limit Register The I/O limit register is used in decoding I/O addresses to pass through the bridge. The bridge supports 32-bit I/O addressing; thus, bits 3–0 are read-only and default to 0001b. The upper four bits are writable and correspond to address bits AD15–AD12. The lower 12 address bits of the I/O limit address are considered FFFh. Thus, the top of the defined I/O address range is aligned on a 4K-byte boundary. The upper 16 address bits of the 32-bit I/O limit address corresponds to the contents of the I/O limit upper 16 bits register (offset 32h, see Section 4.27). Bit 7 6 5 4 3 2 1 0 Name I/O limit Type R/W R/W R/W R/W R R R R Default 0 0 0 0 0 0 0 1 Register: I/O limit Type: Read-only, read/write Offset: 1Dh Default: 01h |
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