PCI2250 datasheet(51/85 Pages) TI

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5–1

5 Extension Registers

The TI extension registers are those registers that lie outside the standard PCI-to-PCI bridge device configuration

space (i.e., registers 40h–FFh in PCI configuration space in the PCI2250). These registers can be accessed through

configuration reads and writes. The TI extension registers add flexibility and performance benefits to the standard

PCI-to-PCI bridge. The TI extension registers are not reset on the transition from D3 to D0.

5.1

Chip Control Register

The chip control register is read/write and has a default value of 00h. This register is used to control the functionality

of certain PCI transactions. See Table 5–1 for a complete description of the register contents.

Bit

Name

Chip control

Type

R/W

Default

Chip control

Type:

Read/Write, Read–only

Offset:

40h

Default:

00h

Table 5–1. Chip Control Register

BIT

TYPE

FUNCTION

7–5

Reserved. Bits 7–5 return 0s when read.

R/W

Memory read prefetch. When cleared, bit 4 enables the memory read prefetch.

0 = Upstream memory reads are enabled (default)

1 = Upstream memory reads are disabled

3–2

Reserved. Bits 3 and 2 return 0s when read.

R/W

Reserved

Reserved. Bit 0 returns 0 when read.

PCI2250 Datasheet(PDF) 51 Page - Texas Instruments