PCI2250 datasheet(29/85 Pages) TI

29 / 85 page

3–5

PCI2250

PCI

Device

S_CLKOUT3

PCI

Device

PCI

Device

PCI

Device

S_CLKOUT2

S_CLKOUT1

S_CLKOUT0

S_CLKOUT4

S_CLK

Figure 3–5. Secondary Clock Block Diagram

3.6

Bus Arbitration

The PCI2250 implements bus request (P_REQ) and bus grant (P_GNT) terminals for primary bus arbitration. Four

secondary bus requests and four secondary bus grants are provided on the secondary of the PCI2250. Five potential

initiators, including the bridge, can be located on the secondary bus. The PCI2250 provides a two-tier arbitration

scheme on the secondary bus for priority bus-master handling.

The two-tier arbitration scheme improves performance in systems in which master devices do not all require the same

bandwidth. Any master that requires frequent use of the bus can be programmed to be in the higher priority tier.

3.6.1

Primary Bus Arbitration

The PCI2250, acting as an initiator on the primary bus, asserts P_REQ when forwarding transactions upstream to

the primary bus. In the upstream direction, as long as a posted write data or a delayed transaction request is in the

queue, the PCI2250 keeps P_REQ asserted. If a target disconnect, a target retry, or a target abort is received in

response to a transaction initiated on the primary bus by the PCI2250, P_REQ is deasserted for two PCI clock cycles.

When the primary bus arbiter asserts P_GNT in response to a P_REQ from the PCI2250, the device initiates a

transaction on the primary bus during the next PCI clock cycle after the primary bus is sampled idle.

When P_REQ is not asserted and the primary bus arbiter asserts P_GNT to the PCI2250, the device responds by

parking the P_AD31–P_AD0 bus, the C/BE3–C/BE0 bus, and primary parity (P_PAR) by driving them to valid logic

levels. If the PCI2250 is parking the primary bus and wants to initiate a transaction on the bus, then it can start the

transaction on the next PCI clock by asserting the primary cycle frame (P_FRAME) while P_GNT is still asserted. If

P_GNT is deasserted, then the bridge must rearbitrate for the bus to initiate a transaction.

3.6.2

Internal Secondary Bus Arbitration

S_CFN controls the state of the secondary internal arbiter. The internal arbiter can be enabled by pulling S_CFN low

or disabled by pulling S_CFN high. The PCI2250 provides four secondary bus request terminals and four secondary

PCI2250 Datasheet(PDF) 29 Page - Texas Instruments

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