HC1S40 datasheet(39/110 Pages) ALTERA

39 / 110 page

Altera Corporation

4–15

September 2008

Operating Conditions

Power

Consumption

Altera offers two ways to calculate power for a design, the Altera® web

power calculator and the power estimation feature in the Quartus® II

software.

The interactive power calculator on the Altera website is typically used

prior to designing the FPGA in order to get a magnitude estimate of the

device power. The Quartus II software power estimation feature allows

designers to apply test vectors against their design for more accurate

power consumption modeling.

In both cases, these calculations should only be used as an estimation of

power, not as a specification.

Timing Closure

The timing numbers in Tables 4–34 to 4–43 are only provided as an

indication of allowable timing for HardCopy Stratix devices. The

Quartus II software provides preliminary timing information for

HardCopy Stratix designs, which can be used as an estimation of the

device performance.

Table 4–32. Stratix Device Capacitance

Note (5)

Symbol

Parameter

Minimum

Typical

Maximum

Unit

CIOTB

Input capacitance on I/O pins in I/O banks 3, 4, 7,

and 8.

11.5

CIOLR

Input capacitance on I/O pins in I/O banks 1, 2, 5,

and 6, including high-speed differential receiver

and transmitter pins.

8.2

CCLKTB

Input capacitance on top/bottom clock input pins:

CLK[4..7] and CLK[12..15].

11.5

CCLKLR

Input capacitance on left/right clock inputs:

CLK1,

CLK3, CLK8, CLK10.

7.8

CCLKLR+

Input capacitance on left/right clock inputs:

CLK0,

CLK2, CLK9, and CLK11.

4.4

Notes to Tables 4–4 through 4–32:

(1)

Drive strength is programmable according to values in the Stratix Architecture chapter of the Stratix Device

Handbook.

(2)

When the

tx_outclock port of the altlvds_tx megafunction is 717 MHz, VOD(m in ) = 235 mV on the output

clock pin.

(3)

Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO.

(4)

VREF specifies the center point of the switching range.

(5)

Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement

accuracy is within ±0.5 pF.

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