LPC1768 datasheet(22/72 Pages) PHILIPS

22 / 72 page

LPC1768_66_65_64_2

Objective data sheet

Rev. 02 — 11 February 2009

22 of 72

NXP Semiconductors

LPC1768/66/65/64

32-bit ARM Cortex-M3 microcontroller

7.13.1 Features

• Two CAN controllers and buses.

• Data rates to 1 Mbit/s on each bus.

• 32-bit register and RAM access.

• Compatible with CAN speciﬁcation 2.0B, ISO 11898-1.

• Global Acceptance Filter recognizes standard (11-bit) and extended-frame (29-bit)

receive identiﬁers for all CAN buses.

• Acceptance Filter can provide FullCAN-style automatic reception for selected

Standard Identiﬁers.

• FullCAN messages can generate interrupts.

7.14 12-bit ADC

The LPC1768/66/65/64 contain one ADC. It is a single 12-bit successive approximation

ADC with eight channels and DMA support.

7.14.1 Features

• 12-bit successive approximation ADC.

• Input multiplexing among 8 pins.

• Power-down mode.

• Measurement range VREFN to Vi(VREFP).

• 12-bit conversion rate: 1 MHz.

• Individual channels can be selected for conversion.

• Burst conversion mode for single or multiple inputs.

• Optional conversion on transition of input pin or Timer Match signal.

• Individual result registers for each ADC channel to reduce interrupt overhead.

• DMA support.

7.15 10-bit DAC (LPC1768/66/65 only)

The DAC allows to generate a variable analog output. The maximum output value of the

DAC is Vi(VREFP).

7.15.1 Features

• 10-bit DAC

• Resistor string architecture

• Buffered output

• Power-down mode

• Selectable output drive

• Dedicated conversion timer

• DMA support

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