SN54ACT8997, SN74ACT8997

SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES

SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS

SCAS157D – APRIL 1990 – REVISED DECEMBER 1996

4

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

NAME

I/O

DESCRIPTION

DCI

I

Device condition input. DCI receives interrupt and protocol signals from the secondary scan path(s). When the

counter register is instructed to count up or down, DCI is configured as the counter clock.

DCO

O

Device condition output. DCO is configured by the control register to output protocol and interrupt signals and can

be configured by the control register to output an error signal if the instruction register is loaded with an invalid value.

DCO is further configured by the control register as:

Active high or active low (reset condition = active low)

Open drain or 3 state (reset condition = open drain)

DTCK

O

Device test clock. DTCK outputs the buffered test clock TCK to the secondary scan path(s).

DTDI1

DTDI2

DTDI3

DTDI4

I

Device test data input 1–4. DTDI1–DTDI4 receive the serial test data output(s) of the selected secondary scan

path(s). An internal pullup forces DTDI1–DTDI4 to a high logic level if it is left unconnected.

DTDO1

DTDO2

DTDO3

DTDO4

O

Device test data output 1–4. These outputs send serial test data to the TDI input(s) of the secondary scan path(s).

DTMS1

DTMS2

DTMS3

DTMS4

O

Device test mode select 1–4. Any combination of these four outputs can be selected to follow TMS to direct the

secondary scan path(s) through the TAP controller states in Figure 1. The unselected DTMS outputs can be set

independently to a high or low logic level. The TMS circuit monitors input from the select register to determine the

configuration of the DTMS outputs.

GND

Ground

IDI

ID2

ID3

ID4

I

Identification 1–4. This 4-bit data bus can be hardwired to provide identification of the subsystem under test. The

value present on the bus can be scanned out through the boundary scan or ID bus registers.

MCI

I

Master condition input. MCI receives interrupt and protocol signals from a primary bus controller (PBC). The level

on MCI is buffered and output on MCO.

MCO

O

Master condition output. MCO transmits interrupt and protocol signals to the secondary scan path(s).

TCK

I

Test clock. One of four terminals required by IEEE Standard 1149.1. All operations of the ’ACT8997 except for the

count function are synchronous to TCK. Data on the device inputs is captured on the rising edge of TCK, and outputs

change on the falling edge of TCK.

TDI

I

Test data input. One of four terminals required by IEEE Standard 1149.1. TDI is the serial input for shifting information

into the instruction register or selected data register. TDI is typically driven by the TDO of the PBC. An internal pullup

forces TDI to a high level if left unconnected.

TDO

O

Test data output. One of four terminals required by IEEE Standard 1149.1. TDO is the serial output for shifting

information out of the instruction register or selected data register. TDO is typically connected to the TDI of the next

scannable device in the primary scan path.

TMS

I

Test mode select. One of four terminals required by IEEE Standard 1149.1. The level of TMS at the rising edge of

TCK directs the ’ACT8997 through its TAP controller states. An internal pullup forces TMS to a high level if left

unconnected.

TRST

I

Test reset. This active-low input implements the optional reset terminal of IEEE Standard 1149.1. When asserted,

TRST causes the ’ACT8997 to go to the Test-Logic-Reset state and configure the instruction register and data

registers to their power-up values. An internal pullup forces TRST to a high level if left unconnected.

VCC

Supply voltage