SN54ACT8997, SN74ACT8997

SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES

SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS

SCAS157D – APRIL 1990 – REVISED DECEMBER 1996

13

POST OFFICE BOX 655303

select register description

The select register (SR) is an 8-bit serial register that determines which, if any, of the secondary scan paths

(SSPs) will be included in the primary scan path. A reset operation forces all bits to a logic 0. The register is

divided into four 2-bit sections, each of which controls one SSP. Figure 4 shows the mapping of the bits to the

SSPs and the order of scan. For each SSP, the higher-order bit is the MSB and the lower-order bit is the LSB

(e.g., bit 3 is the MSB of SSP2 and bit 2 is the LSB of SSP2).

TDO

Bit 7

(MSB)

TDI or DTDI

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

SSP4

SSP3

SSP2

SSP1

Figure 4. Select Register Bits and Order of Scan

When a new 8-bit value is loaded into the SR, the configuration of one or more DTMS pins may change. If the

new value of the SR configures a DTMS pin to a static (high or low) level, it assumes that level on the falling

edge of TCK in the Update-DR TAP state. This condition is independent of any previous SR configurations. If

the new value of the SR forces a DTMS pin to follow TMS (i.e., select the secondary scan path) and one or more

DTMS pins are currently in the TMS-follow mode, the transfer of DTMS lines occurs on the falling edge of TCK

in the Update-DR TAP state. If, however, the new configuration forces a DTMS pin to follow TMS while no other

DTMS pin is selected, the DTMS pin is forced low and does not begin following TMS until the falling edge of

TCK in the Run-Test/Idle TAP state; therefore, when an SSP is initially selected, the TAP state should travel from

Update-DR to Run-Test /Idle, not from Update-DR to Select-DR-Scan.

Although any combination of SSPs can be selected, the order of scan for each combination is fixed (see data

flow description for details). The SR bit decoding is shown in Table 7.

Table 7. Select Register-Bit Decoding

MSB

LSB

DTMS

SOURCE

DTDO

STATUS

0

0

H

Z

0

1

L

Z

1

X

TMS

Active†

† The DTDO1–4 outputs are active only in

the Shift-IR and Shift-DR TAP states.