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LTC2209 Datasheet(PDF) 1 Page - Linear Technology |
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LTC2209 Datasheet(HTML) 1 Page - Linear Technology |
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1 / 32 page  LTC2209 1 2209fa 16-Bit, 160Msps ADC The LTC®2209 is a 160Msps 16-bit A/D converter designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 700MHz. The input range of the ADC can be optimized with the PGA front end. The LTC2209 is perfect for demanding communications applications, with AC performance that includes 77.3dBFS Noise Floor and 100dB spurious free dynamic range (SFDR). Ultra low jitter of 70fsRMS allows undersampling of high input frequencies with excellent noise performance. Maximum DC specs include ±5LSB INL, ±1LSB DNL (no missing codes). The digital output can be either differential LVDS or single-ended CMOS. There are two format options for the CMOS outputs: a single bus running at the full data rate or demultiplexed busses running at half data rate. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V. The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer al- lows high performance at full speed with a wide range of clock duty cycles. n Telecommunications n Receivers n Cellular Base Stations n Spectrum Analysis n Imaging Systems n ATE n Sample Rate: 160Msps n 77.3dBFS Noise Floor n 100dB SFDR n SFDR >84dB at 250MHz (1.5VP-P Input Range) n PGA Front End (2.25VP-P or 1.5VP-P Input Range) n 700MHz Full Power Bandwidth S/H n Optional Internal Dither n Optional Data Output Randomizer n LVDS or CMOS Outputs n Single 3.3V Supply n Power Dissipation: 1.45W n Clock Duty Cycle Stabilizer n Pin-Compatible Family: 130Msps: LTC2208 (16-Bit), LTC2208-14 (14-Bit) 105Msps: LTC2217 (16-Bit) n 64-Pin (9mm × 9mm) QFN Package 64k Point FFT, fIN = 15.1MHz, –1dBFS, PGA = 0 FEATURES APPLICATIONS DESCRIPTION TYPICAL APPLICATION L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. – + S/H AMP CORRECTION LOGIC AND SHIFT REGISTER OUTPUT DRIVERS 16-BIT PIPELINED ADC CORE INTERNAL ADC REFERENCE GENERATOR 1.25V COMMON MODE BIAS VOLTAGE CLOCK/DUTY CYCLE CONTROL D15 • • • D0 PGA SHDN DITH MODE LVDS RAND VCM ANALOG INPUT 2209 TA01 CMOS OR LVDS 0.5V TO 3.6V 3.3V 3.3V SENSE OGND OVDD 2.2μF 1μF 1μF 1μF 1μF VDD GND ADC CONTROL INPUTS AIN+ ENC + AIN– ENC – OF CLKOUT FREQUENCY (MHz) 0 –100 –30 –20 –10 0 20 40 50 2209 TA01b –120 –60 –80 –110 –40 –50 –130 –70 –90 10 30 70 60 80 |
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