TL16C554, TL16C554I

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D – JANUARY 1994 – REVISED JULY 1998

7

POST OFFICE BOX 655303

read cycle timing requirements over recommended ranges of operating free-air temperature and

supply voltage (see Figure 4)

MIN

MAX

UNIT

tw4

Pulse duration, IOR low

75

ns

tsu1

Setup time, CSx valid before IOR low (see Note 2)

10

ns

tsu2

Setup time, A2 – A0 valid before IOR low (see Note 2)

15

ns

th1

Hold time, A2 – A0 valid after IOR high (see Note 2)

0

ns

th2

Hold time, CSx valid after IOR high (see Note 2)

0

ns

td1

Delay time, tsu2 + tw4 + td2 (see Note 3)

140

ns

td2

Delay time, IOR high to IOR or IOW low

50

ns

NOTES:

2. The internal address strobe is always active.

3. In the FIFO mode, td1 = 425 ns (min) between reads of the receiver FIFO and the status registers (interrupt identification register

and line status register).

write cycle timing requirements over recommended ranges of operating free-air temperature and

supply voltage (see Figure 5)

MIN

MAX

UNIT

tw5

Pulse duration, IOW

↓

50

ns

tsu3

Setup time, CSx valid before IOW

↓ (see Note 2)

10

ns

tsu4

Setup time, A2 – A0 valid before IOW

↓ (see Note 2)

15

ns

tsu5

Setup time, D7 – D0 valid before IOW

↑

10

ns

th3

Hold time, A2 – A0 valid after IOW

↑ (see Note 2)

5

ns

th4

Hold time, CSx valid after IOW

↑ (see Note 2)

5

ns

th5

Hold time, D7 – D0 valid after IOW

↑

25

ns

td3

Delay time, tsu4 + tw5 + td4

120

ns

td4

Delay time, IOW

↑ to IOW or IOR↓

55

ns

NOTE 2: The internal address strobe is always active.

read cycle switching characteristics over recommended ranges of operating free-air temperature

PARAMETER

MIN

MAX

UNIT

ten

Enable time, IOR

↓ to D7–D0 valid

30

ns

tdis

Disable time, IOR

↑ to D7–D0 released

0

20

ns

NOTE 4: VOL and VOH (and the external loading) determine the charge and discharge time.