TL16C554, TL16C554I

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D – JANUARY 1994 – REVISED JULY 1998

21

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

line control register (LCR) (continued)

Word Length

Select

0

0 = 5 Data Bits

0

1 = 6 Data Bits

1

0 = 7 Data Bits

1

1 = 8 Data bits

LINE CONTROL REGISTER

LCR

7

LCR

6

LCR

5

LCR

4

LCR

3

LCR

2

LCR

1

LCR

0

Stop Bit

Select

0 = 1 Stop Bit

1 = 1.5 Stop Bits if 5 Data Bits Selected

2 Stop Bits if 6, 7, 8 Data Bits Selected

Parity Enable

0 = Parity Disabled

1 = Parity Enabled

Even Parity

Select

0 = Odd Parity

1 = Even Parity

Stick Parity

0 = Stick Parity Disabled

1 = Stick Parity Enabled

Break Control

0 = Break Disabled

1 = Break Enabled

Divisor Latch

Access BIt

0 = Access Receiver Buffer

1 = Access Divisor Latches

Figure 15. Line Control Register Contents

line status register (LSR)

The LSR is a single register that provides status indicators. The LSR shown in Table 6 is described in the

following bulleted list:

transferred into the receiver buffer register or the FIFO. LSR0 is cleared by a CPU read of the data in the

receiver buffer register or the FIFO.

is not read by the CPU before the next character is transferred into the receiver buffer register overwriting

the previous character. The OE indicator is cleared whenever the CPU reads the contents of the LSR. An

overrun error occurs in the FIFO mode after the FIFO is full and the next character is completely received.

The overrun error is detected by the CPU on the first LSR read after it happens. The character in the shift

register is not transferred to the FIFO, but it is overwritten.

have the correct parity as selected by LCR3 and LCR4. The PE bit is set upon detection of a parity error

and is cleared when the CPU reads the contents of the LSR. In the FIFO mode, the parity error is associated

with a particular character in the FIFO. LSR2 reflects the error when the character is at the top of the FIFO.

a valid stop bit. LSR3 is set when the stop bit following the last data bit or parity bit is detected as a zero

bit (spacing level). The FE indicator is cleared when the CPU reads the contents of the LSR. In the FIFO

mode, the framing error is associated with a particular character in the FIFO. LSR3 reflects the error when

the character is at the top of the FIFO.