TL16C554FN datasheet(20/33 Pages) TI

20 / 33 page

TL16C554, TL16C554I

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D – JANUARY 1994 – REVISED JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

interrupt identification register (IIR) (continued)

D Bit 0: IIR0 indicates whether an interrupt is pending. When IIR0 is cleared, an interrupt is pending.

D Bits 1 and 2: IIR1 and IIR2 identify the highest priority interrupt pending as indicated in Table 5.

D Bit 3: IIR3 is always cleared when in the TL16C450 mode. This bit is set along with bit 2 when in the FIFO

mode and a trigger change level interrupt is pending.

D Bits 4 and 5: IIR4 and IIR5 are always cleared.

D Bits 6 and 7: IIR6 and IIR7 are set when FCR0 = 1.

line control register (LCR)

The format of the data character is controlled by the LCR. The LCR may be read. Its contents are described

in the following bulleted list and shown in Figure 15.

D Bits 0 and 1: LCR0 and LCR1 are word length select bits. These bits program the number of bits in each

serial character and are shown in Figure 15.

D Bit 2: LCR2 is the stop bit select bit. This bit specifies the number of stop bits in each transmitted character.

The receiver always checks for one stop bit.

D Bit 3: LCR3 is the parity enable bit. When LCR3 is set, a parity bit between the last data word bit and stop

bit is generated and checked.

D Bit 4: LCR4 is the even parity select bit. When this bit is set and parity is enabled (LCR3 is set), even parity

is selected. When this bit is cleared and parity is enabled, odd parity is selected.

D Bit 5: LCR5 is the stick parity bit. When parity is enabled (LCR3 is set) and this bit is set, the transmission

and reception of a parity bit is placed in the opposite state from the value of LCR4. This forces parity to a

known state and allows the receiver to check the parity bit in a known state.

D Bit 6: LCR6 is a break control bit. When this bit is set, the serial outputs TXx are forced to the spacing state

(low). The break control bit acts only on the serial output and does not affect the transmitter logic. If the

following sequence is used, no invalid characters are transmitted because of the break.

Step 1.

Load a zero byte in response to the transmitter holding register empty (THRE) status indicator.

Step 2.

Set the break in response to the next THRE status indicator.

Step 3.

Wait for the transmitter to be idle when transmitter empty status signal is set (TEMT = 1); then

clear the break when the normal transmission has to be restored.

D Bit 7: LCR7 is the divisor latch access bit (DLAB) bit. This bit must be set to access the divisor latches DLL

and DLM of the baud rate generator during a read or write operation. LCR7 must be cleared to access the

receiver buffer register, the transmitter holding register, or the interrupt enable register.

TL16C554FN Datasheet(PDF) 20 Page - Texas Instruments