TL16C554, TL16C554I

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D – JANUARY 1994 – REVISED JULY 1998

15

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

Three types of information are stored in the internal registers used in the ACE: control, status, and data. Mnemonic

abbreviations for the registers are shown in Table 1. Table 2 defines the address location of each register and whether

it is read only, write only, or read writable.

Table 1. Internal Register Mnemonic Abbreviations

CONTROL

MNEMONIC

STATUS

MNEMONIC

DATA

MNEMONIC

Line control register

LCR

Line status register

LSR

Receiver buffer register

RBR

FIFO control register

FCR

Modem status register

MSR

Transmitter holding register

THR

Modem control register

MCR

Divisor latch LSB

DLL

Divisor latch MSB

DLM

Interrupt enable register

IER

DLAB‡

A2§

A1§

A0§

READ MODE

WRITE MODE

0

0

0

0

Receiver buffer register

Transmitter holding register

0

001

Interrupt enable register

X

0

1

0

Interrupt identification register

FIFO control register

X

011

Line control register

X

100

Modem control register

X

1

0

1

Line status register

X

1

1

0

Modem status register

X

1

1

1

Scratchpad register

Scratchpad register

1

000

LSB divisor latch

1

0

0

1

MSB divisor latch

X = irrelevant, 0 = low level, 1 = high level

† The serial channel is accessed when either CSA or CSD is low.

‡ DLAB is the divisor latch access bit and bit 7 in the LCR.

§ A2 – A0 are device terminals.

Individual bits within the registers with the bit number in parenthesis are referred to by the register mnemonic. For

example, LCR7 refers to line control register bit 7. The transmitter buffer register and receiver buffer register are data

registers that hold from five to eight bits of data. If less than eight data bits are transmitted, data is right justified to

the LSB. Bit 0 of a data word is always the first serial data bit received and transmitted. The ACE data registers are

double buffered (TL16450 mode) or FIFO buffered (FIFO mode) so that read and write operations can be performed

when the ACE is performing the parallel-to-serial or serial-to-parallel conversion.