TL16C554FN datasheet(17/33 Pages) TI

17 / 33 page

TL16C554, TL16C554I

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D – JANUARY 1994 – REVISED JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

FIFO control register (FCR)

The FCR is a write-only register at the same location as the IIR. It enables the FIFOs, sets the trigger level of

the receiver FIFO, and selects the type of DMA signalling.

D Bit 0: FCR0 enables the transmit and receiver FIFOs. All bytes in both FIFOs can be cleared by clearing

FCR0. Data is cleared automatically from the FIFOs when changing from the FIFO mode to the TL16C450

mode (see FCR bit 0) and vice versa. Programming of other FCR bits is enabled by setting FCR0.

D Bit 1: When set, FCR1 clears all bytes in the receiver FIFO and resets its counter. This does not clear the

shift register.

D Bit 2: When set, FCR2 clears all bytes in the transmit FIFO and resets the counter. This does not clear the

shift register.

D Bit 3: When set, FCR3 changes RXRDY and TXRDY from mode 0 to mode 1 if FCR0 is set.

D Bits 4 and 5: FCR4 and FCR5 are reserved for future use.

D Bits 6 and 7: FCR6 and FCR7 set the trigger level for the receiver FIFO interrupt (see Table 4).

Table 4. Receiver FIFO Trigger Level

BIT

RECEIVER FIFO

TRIGGER LEVEL (BYTES)

FIFO interrupt mode operation

The following receiver status occurs when the receiver FIFO and receiver interrupts are enabled.

LSR0 is set when a character is transferred from the shift register to the receiver FIFO. When the FIFO is

empty, it is reset.

IIR = 06 receiver line status interrupt has higher priority than the receive data available interrupt

IIR = 04.

Receive data available interrupt is issued to the CPU when the programmed trigger level is reached by the

FIFO. As soon as the FIFO drops below its programmed trigger level, it is cleared.

IIR = 04 (receive data available indicator) also occurs when the FIFO reaches its trigger level. It is cleared

when the FIFO drops below the programmed trigger level.

The following receiver FIFO character time-out status occurs when receiver FIFO and receiver interrupts are

enabled.

TL16C554FN Datasheet(PDF) 17 Page - Texas Instruments