TL16PIR552 datasheet(42/52 Pages) TI

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TL16PIR552

DUAL UART WITH DUAL IrDA AND

1284 PARALLEL PORT

SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

Table 14. Mode Summary

MODE

DESCRIPTION

000

Centronics (default) mode, forward direction only

001

Bidirectional Centronics mode

010

Parallel port data FIFO mode

011

ECP Parallel port mode

100

EPP mode

110

Test mode

111

Configuration mode

mode switching

Mode switching is only allowed into and out of the modes 000 and 001. All 1284 negotiation takes place in these

two modes. Setting the mode to 011 (ECP Parallel Port mode) causes the hardware to initiate data transfer.

Switching out of modes 011 and 010 in the middle of a transfer or when data remains in the FIFO causes the

transfer to be aborted and the data to be lost.

data compression

The TL16PIR552 supports run length encoded (RLE) decompression in hardware and can transfer compressed

data to a peripheral. Run length encoded (RLE) compression in hardware is not supported. To transfer

compressed data in ECP mode, the compression count is written to the ECPAFIFO and a data byte is written

to the ECPDFIFO.

Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many

times the next byte is to be repeated. Decompression simply intercepts the RLE byte and repeats the following

byte the specified number of times. When a run-length count is received from a peripheral, the subsequent data

byte is replicated that specified number of times. A run-length count of zero specifies that only one byte of data

is represented by the next data byte. A run-length count of 127 indicates that the next byte should be expanded

to 128 bytes. To prevent data expansion, however, run-length counts of zero should be avoided.

The RLE command byte is loaded to the FIFO. Then the logic offloads this command to the decompression

counter to generate the correct number of decompressed data available. The logic asserts PDRQ only when

there are data bytes in the FIFO. Although the command byte is loaded to the FIFO, the PDRQ is not asserted.

TL16PIR552 Datasheet(PDF) 42 Page - Texas Instruments

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