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TL16PIR552 Datasheet(PDF) 17 Page - Texas Instruments |
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TL16PIR552 Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 52 page ![]() TL16PIR552 DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996 17 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION td7 (see Note A) td8 Stop Sample Clock SINx (first byte) Active IOR (IOR RBR) RXRDYx (see Note A) 50% 50% 50% NOTE A: For a timeout interrupt, td7 = 9 RCLKs. Figure 10. Receiver Ready (RXRDY), FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0) td7 (see Note A) td8 Sample Clock SINx (first byte that reaches the trigger level) Active IOR (IOR RBR) RXRDYx (see Note A) 50% 50% 50% NOTES: A. This is the reading of the last byte in the FIFO. B. For a timeout interrupt, td7 = 9 RCLKs. Figure 11. Receiver Ready (RXRDY), FCR0 = 1 or FCR3 = 1 (Mode 1) |
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