TL16PIR552 datasheet(33/52 Pages) TI

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TL16PIR552

DUAL UART WITH DUAL IrDA AND

1284 PARALLEL PORT

SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

modem status register (MSR) (continued)

Bit 2: Trailing edge-of-the-ring indicator (TERI) detector. TERI indicates that the RI input to the chip has changed

from a low to a high level. When TERI is set to 1 and the modem status interrupt is enabled, a modem status

interrupt is generated.

Bit 3: Change in data carrier detect (

∆DCD) indicator. ∆DCD indicates that the DCD input to the chip has

changed state since the last time it was read by the CPU. When

∆DCD is set to 1 and the modem status interrupt

is enabled, a modem status interrupt is generated.

Bit 4: Complement of the clear to send (CTS) input. When the UART is in the diagnostic test mode (LOOP

[MCR4] = 1), this bit is equal to the modem control register bit 1 (RTS).

Bit 5: Complement of the data set ready (DSR) input. When the UART is in the diagnostic test mode (LOOP

[MCR4] = 1), this bit is equal to the modem control register bit 0 (DTR).

Bit 6: Complement of the ring indicator (RI) input. When the UART is in the diagnostic test mode (LOOP

[MCR4] = 1), this bit is equal to the modem control register bit 2 (OUT1).

Bit 7: Complement of the data carrier detect (DCD) input. When the UART is in the diagnostic test mode (LOOP

[MCR4] = 1), this bit is equal to the modem control register bit 3 (OUT2).

scratch register (SCR)

The scratch register is an 8-bit register that is intended for programmer use as a scratchpad in the sense that

it temporarily holds the programmer data without affecting any other UART operation.

prescaler

When DLAB = 1, the six least significant bits of the scratch register contain the prescaler value. IR logic is

selected when the seventh bit is set to 1. Otherwise UART output is selected. After reset, UART0 is in IR mode

and UART1 is in UART mode.

prescaler descriptions

The clock prescaler allows for the divisor from 0 to 31.5 in 0.5 increments (scr(0) is the half-bit divider). The

divisor value is loaded from scratch register with DLAB = 1. The output of the divisor feeds the UART clock. A

programmed divisor between 2 and 7.5 drives the UART clock low for one XIN clock cycle for integer divisor

and 1.5 XIN clock cycles for integer-plus a half clock divisor. A programmed divisor of eight or greater drives

the UART clock low for four XIN clock cycles for integer divisors and 4.5 XIN clock cycles for integer-plus-a-half

divisor. Based on the above parameters, the acceptable XIN/divisor combinations can be derived. The precision

of the programmable clock generator for integer-plus-a-half divisor depends on the closeness to a 50% duty

cycle for the XIN input clock.

Example: When the oscillator frequency is 22 Mhz (see Table 9).

Table 9. Typical Prescaler Example

XIN

PRESCALER DIVISOR

UART CLOCK

UART DIVISOR

BAUD RATE

22.118 Mhz

5.5

4 Mhz

31.25k

22.118 Mhz

7.33 Mhz

458K

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