TMS320C206, TMS320LC206

DIGITAL SIGNAL PROCESSORS

SPRS065B – JUNE 1998 – REVISED JANUARY 1999

42

POST OFFICE BOX 1443

CLOCK CHARACTERISTICS AND TIMING

clock options

PARAMETER

DIV2

DIV1

Internal divide-by-two with external crystal or external oscillator

0

0

PLL multiply-by-one

0

1

PLL multiply-by-two

1

0

PLL multiply-by-four

1

1

The internal oscillator is enabled by connecting a crystal across X1 and CLKIN/X2. The crystal should be in

either fundamental or overtone operation and parallel resonant, with an effective series resistance of 30

Ω and

a power dissipation of 1 mW; it should be specified at a load capacitance of 20 pF. Note that overtone crystals

require an additional tuned-LC circuit. Figure 9 shows an external crystal (fundamental frequency) connected

to the on-chip oscillator.

X1

CLKIN/X2

C1

C2

Crystal

NOTE A: Texas Instruments encourages customers to submit samples of the device to the resonator/crystal vendor for full characterization.

Figure 9. Internal Clock Option

† PLL modes can also be used with the on-chip oscillator. However, in this case, the PLL lock time should be based on stable clock from the on-chip

oscillator.