TMS320C206 datasheet(13/58 Pages) TI

13 / 58 page

TMS320C206, TMS320LC206

DIGITAL SIGNAL PROCESSORS

SPRS065B – JUNE 1998 – REVISED JANUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

input scaling shifter

The TMS320C206/TMS320LC206 provides a scaling shifter with a 16-bit input connected to the data bus and

a 32-bit output connected to the CALU. This shifter operates as part of the path of data coming from program

or data space to the CALU, and requires no cycle overhead. It is used to align the 16-bit data coming from

memory to the 32-bit CALU. This is necessary for scaling arithmetic as well as aligning masks for logical

operations.

The scaling shifter produces a left shift of 0 to 16 on the input data. The LSBs of the output are filled with zeros;

the MSBs may either be filled with zeros or sign-extended, depending upon the value of the SXM bit

(sign-extension mode) of status register ST1. The shift count is specified by a constant embedded in the

instruction word or by a value in TREG. The shift count in the instruction allows for specific scaling or alignment

operations specific to that point in the code. The TREG base shift allows the scaling factor to adapt to the

performance of the system.

multiplier

The TMS320C206/TMS320LC206 uses a 16 x16-bit hardware multiplier that is capable of computing a signed

or an unsigned 32-bit product in a single machine cycle. All multiply instructions, except the MPYU (multiply

unsigned) instruction, perform a signed-multiply operation. That is, two numbers being multiplied are treated

as 2s-complement numbers, and the result is a 32-bit 2s-complement number. There are two registers

associated with the multiplier:

D a 16-bit temporary register (TREG) that holds one of the operands for the multiplier, and

D a 32-bit product register (PREG) that holds the product.

Four product shift modes (PM) are available at the PREG output (PSCALE). These shift modes are useful for

performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products.

The PM field of status register ST1 specifies the PM shift mode, as shown in Table 5.

Table 5. PSCALE Product Shift Modes

SHIFT

DESCRIPTION

no shift

Product fed to CALU or data bus with no shift

left 1

Removes the extra sign bit generated in a 2s-complement multiply to produce a Q31 product

left 4

Removes the extra four sign bits generated in a 16 x13 2s-complement multiply to a produce a Q31

product when using the multiply by a 13-bit constant

right 6

Scales the product to allow up to 128 product accumulation without the possibility of accumulator overflow

The product can be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit

2s-complement numbers (MPY). A four-bit shift is used in conjunction with the MPY instruction with a short

immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number by

a 13-bit number. Finally, the output of PREG can be right-shifted six bits to enable the execution of up to

128 consecutive multiply/accumulates without the possibility of overflow.

The LT (load TREG) instruction normally loads TREG to provide one operand (from the data bus), and the MPY

(multiply) instruction provides the second operand (also from the data bus). A multiplication can also be

performed with a 13-bit immediate operand when using the MPY instruction. A product is then obtained every

two cycles. For efficient implementation of multiple products, or multiple sums of products, the CPU provides

pipelining of the TREG load operation with certain CALU operations which use the PREG. These operations

include: load ACC with PREG (LTP); add PREG to ACC (LTA); add PREG to ACC and shift TREG input data

to next address in data memory (LTD); and subtract PREG from ACC (LTS).

TMS320C206 Datasheet(PDF) 13 Page - Texas Instruments

TMS320C206 Datasheet(HTML) 13 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

Datasheet Download

Link URL