TMS320C206 datasheet(21/58 Pages) TI

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TMS320C206, TMS320LC206

DIGITAL SIGNAL PROCESSORS

SPRS065B – JUNE 1998 – REVISED JANUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

on-chip registers

The TMS320C206/TMS320LC206 includes three registers mapped to internal data space and sixteen (16)

registers mapped to internal I/O space. Table 9 describes these registers and shows their respective addresses.

In the table, DS† refers to data space and IS† refers to I/O space.

Table 9. On-Chip Memory and I/O Mapped Registers

NAME

ADDRESS†

VALUE AT

RESET‡

DESCRIPTION

IMR

DS@0004

0000h

Interrupt-mask register. This seven-bit register individually masks or enables the seven

interrupts. Bit 0 shares external interrupt INT1 and HOLD. INT2 and INT3 share bit 1. Bit 2

ties to the timer interrupt, TINT. Bits 3 and 4, RINT and XINT, respectively, are for the

synchronous serial port, SSP. Bit 5, TXRXINT, shares the transmit and receive interrupts for

the asynchronous serial port, ASP. Bit 6 is reserved for monitor-mode-emulation operations

and must always be set to 0 except in conjunction with emulation-monitor operations. Bits

7 – 15 are not used in the TMS320C206/TMS320LC206. IMR is set to 0 at reset. A bit value

of 0 disables an interrupt, and a value of 1 enables an interrupt.

GREG

DS@0005

0000h

Global-memory allocation register. This 8-bit register specifies the size of the global memory

space. GREG is set to 0 at reset.

IFR

DS@0006

0000h

Interrupt-flag register. The seven-bit IFR indicates that the TMS320C206/TMS320LC206

has latched an interrupt from one of the seven maskable interrupts. Bit 0 shares external

interrupt INT1 and HOLD. INT2 and INT3 share bit 1. Bit 2 ties to the timer interrupt, TINT.

Bits 3 and 4, RINT and XINT, respectively, are for the SSP. Bit 5, TXRXINT, shares the

transmit and receive interrupts for the ASP. Bit 6 is reserved for monitor-mode-emulation

operations and must always be set to 0 except in conjunction with emulation-monitor

operations. Writing a 1 to the respective interrupt bit clears an active flag and the respective

pending interrupt. Writing a 1 to an inactive flag has no effect. Bits 7 – 15 are not used in the

TMS320C206/TMS320LC206. IFR is set to 0 at reset.

PMST

IS@FFE4

0006h

Bit 0 - Processor mode status bit (PMST). latches in the MP/MC pin at reset. This bit can

be written to configure microprocessor (1) or microcomputer mode (0). Bits 1 and 2

configure the SARAM mapping either in program memory, data memory, or both. At

reset, these bits are 11, the SARAM is mapped in both program and data space.

DON (bit 2)

PON (bit 1)

- SARAM not mapped, address in external

memory

- SARAM in on-chip program memory at 0x8000h

- SARAM in on-chip data memory at 0x800h

- SARAM in on-chip program and data memory

(reset value)

Bit 3 - LEVEXT8 bit. This bit captures the status of the EXT8 pin 1 at reset only.

Bit 15 – Fast RD, FRDN. This bit provides software control to select an inverted R/W

signal in place of the RD signal (pin 45). This is intended to help achieve zero wait-state

memory interface with slow memory devices. At reset, this bit is 0 and selects RD as the

signal at pin 45. If the FRDN bit is written with a 1, the read signal at pin 45 is replaced

with the inverted R/W signal.

CLK

IS@FFE8

0000h

CLKOUT1 on or off. At reset, this bit is configured as a zero for the CLKOUT1 pin to be active.

If this bit is a 1, CLKOUT1 pin is turned off.

ICR

IS@FFEC

0000h

Interrupt-control register. This register is used to determine which interrupt is active since

INT1 and HOLD share the same interrupt vector as INT2 and INT3. A portion of this register

is for mask/unmask (similar to IFR). At reset, all bits are zeroed, thereby allowing the HOLD

mode to be enabled. The MODE bit is used by the hold-generating circuit to determine if a

HOLD or INT1 is active.

† DS = data space and IS = input/output ports

‡ ‘x’ indicates undefined or value based on the pin levels at reset.

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