TMS320UC5409 datasheet(22/74 Pages) TI

22 / 74 page

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

Table 5. Pin Control Register (PCR) Bit Field Description (Continued)

BIT

FUNCTION

NAME

SCLKME

Sample rate clock mode extended

SCLKME = 0

External clock via CLKS or CPU clock is used as a reference by the sample rate

generator.

SCLKME = 1

External clock via CLKR or CLKX clock is used as a reference by the sample rate

generator.

CLKS

STAT

CLKS pin status. CLKS STAT reflects value on CLKS pin when selected as a general-purpose input.

DX STAT

DX pin status. DX STAT reflects value on DX pin when it is selected as a general-purpose output.

DR STAT

DR pin status. DR STAT reflects value on DR pin when it is selected as a general-purpose input.

3–2

FSXP

Receive/Transmit frame synchronization polarity.

3 – 2

FSRP

FS(R/X)P = 0

Frame synchronization pulse FS(R/X) is active high

FS(R/X)P = 1

Frame synchronization pulse FS(R/X) is active low

CLKXP

Transmit clock polarity

CLKXP = 0

Transmit data sampled on rising edge of CLKR

CLKXP = 1

Transmit data sampled on falling edge of CLKR

CLKRP

Receive clock polarity

CLKRP = 0

Receive data sampled on falling edge of CLKR

CLKRP = 1

Receive data sampled on rising edge of CLKR

The ’5409 sample rate generator has four clock input options that are only available when both the PCR and

SRGR2 are used. Table 6 shows the sample rate generator clock input options.

Table 6. Sample Rate Generator Clock Input Options

MODE

SCLKME

(PCR.7)

CLKSM

(SRGR2.13)

CLKS pin

CPU

CLKR pin

CLKX pin

GSYNC

CLKSP

CLKSM

FSGM

FPER

Legend: R = Read, W = Write

Figure 9. Sample Rate Generator Register 2 (SRGR2)

sample rate generator external clock options (continued)

TMS320UC5409 Datasheet(PDF) 22 Page - Texas Instruments

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