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TMS320UC5409 Datasheet(PDF) 28 Page - Texas Instruments

Part # TMS320UC5409
Description  FIXED-POINT DIGITAL SIGNAL PROCESSOR
PDF  74 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320UC5409 Datasheet(HTML) 28 Page - Texas Instruments

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TMS320UC5409
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS101A – APRIL 1999 – REVISED AUGUST 1999
28
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
DMA interrupts
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is
determined by the IMOD and DINM bits in the DMA channel mode control register (DMMCRn). The available
modes are shown in Table 9.
Table 9. DMA Interrupts
MODE
DINM
IMOD
INTERRUPT
ABU (non-decrement)
1
0
At full buffer only
ABU (non-decrement)
1
1
At half buffer and full buffer
Multi-Frame
1
0
At block-transfer complete (DMCTRn = DMSEFCn[7:0] = 0)
Multi-Frame
1
1
At end of frame and end of block (DMCTRn = 0)
Either
0
X
No interrupt generated
Either
0
X
No interrupt generated
DMA controller synchronization events
The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN bit
field of the DMSEFCn register selects the synchronization event for a channel. The list of possible events and
the DSYN values are shown in Table 10.
Table 10. DMA Synchronization Events
DSYN VALUE
DMA SYNCHRONIZATION EVENT
0000b
No synchronization used
0001b
McBSP0 receive event
0010b
McBSP0 transmit event
0011b
McBSP2 receive event
0100b
McBSP2 transmit event
0101b
McBSP1 receive event
0110b
McBSP1 transmit event
0111b
Reserved
1000b
Reserved
1001b
Reserved
1010b
Reserved
1011b
Reserved
1100b
Reserved
1101b
Timer interrupt event
1110b
External interrupt 3
1111b
Reserved



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