TMS320UC5409 datasheet(25/74 Pages) TI

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TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

DMA controller

The ’UC5409 direct memory access (DMA) controller transfers data between points in the memory map without

intervention by the CPU. The DMA controller allows movements of data to and from internal program/data

memory, internal peripherals (such as the McBSPs), and external program/data memory to occur in the

background of CPU operation. The DMA has six independent programmable channels allowing six different

contexts for DMA operation.

features

The DMA has the following features:

D The DMA has external memory access.

D The DMA operates independently of the CPU.

D The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.

D The DMA has higher priority than the CPU for internal accesses.

D Each channel has independently programmable priorities.

D Each channel’s source and destination address registers can have configurable indexes through memory

on each read and write transfer, respectively. The address may remain constant, be post-incremented,

post-decremented, or be adjusted by a programmable value.

D Each read or write transfer may be initialized by selected events. (Internally only)

D Each DMA channel is capable of sending interrupts to the CPU.

D The DMA can perform double-word transfers (a 32-bit transfer of two 16-bit words). (Internally only)

DMA external access

The ’UC5409 DMA supports external accesses to extended program, data memory, and extended I/O memory.

D Only two channels are available for external accesses. (One for external reads/one for external writes.)

D Single-word transfers are supported for external accesses.

D The DMA does not support transfers from peripherals to external memory.

D The DMA does not support transfers from external memory to the peripherals.

DMA external transfer

Unlike the ’5410, the ’5409 DMA mode control register (DMMCRx) has two additional bits; DLAXS

(DMMCRn[5]) and SLAXS (DMMCRn[11]). These new bits specify the on/off-chip memory for the source and

destination of the program/data/IO spaces.

D When DLAXS is set to 0 (default), the DMA does not perform an external access for the destination. When

DLAXS is set to 1, the DMA performs an external access to the destination location.

D When SLAXS is set to 0 (default), the DMA does not perform an external access for the source. When

DLAXS is set to 1, the DMA performs an external access from the source location.

Two new registers are added to the ’5409 DMA to support DMA accesses to/from DMA extended data memory,

page 1 to page 127.

D The DMA extended source data page register (XSRCDP[6:0]) is located at subbank address 028h.

D The DMA extended destination data page register (XDSTDP[6:0]) is located at subbank address 029h.

TMS320UC5409 Datasheet(PDF) 25 Page - Texas Instruments

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