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TMS418160ADZ Datasheet(PDF) 1 Page - Texas Instruments |
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TMS418160ADZ Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 24 page ![]() TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 This data sheet is applicable to TMS418160As symbolized by Revision “E” and subsequent revisions as described in the device symbolization section. D Organization...1048576 by 16 Bits D Single 5-V Power Supply (± 10% Tolerance) D 1024-Cycle Refresh in 16 ms D Performance Ranges: ACCESS ACCESS ACCESS READ/ TIME TIME TIME WRITE tRAC tCAC tAA CYCLE MAX MAX MAX MIN ’418160A-50 50 ns 13 ns 25 ns 90 ns ’418160A-60 60 ns 15 ns 30 ns 110 ns ’418160A-70 70 ns 18 ns 35 ns 130 ns D Enhanced Page-Mode Operation With xCAS-Before-RAS ( xCBR ) Refresh D 3-State Unlatched Output D Low Power Dissipation D High-Reliability Plastic 42-Lead 400-Mil-Wide Surface-Mount Small-Outline J-Lead (SOJ) Package (DZ Suffix) D Ambient Temperature Range 0 °C to 70°C description The TMS418160A is a 16 777 216-bit dynamic random-access memory (DRAM) device orga- nized as 1 048 576 words of 16 bits. It employs state-of-the-art technology for high performance, reliability, and low power at low cost. This device features maximum RAS access times of 50-, 60-, and 70 ns. All address and data-in lines are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility. The TMS418160A is offered in a 42-lead plastic surface-mount SOJ package (DZ suffix). This package is designed for operation from 0 ° to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PIN NOMENCLATURE A[0 :9] Address Inputs DQ[0:15] Data In / Data Out LCAS Lower Column-Address Strobe UCAS Upper Column-Address Strobe NC No Internal Connection OE Output Enable RAS Row-Address Strobe VDD 5-V Supply VSS Ground W Write Enable 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VDD DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 NC NC W RAS NC NC A0 A1 A2 A3 VDD VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS DZ PACKAGE ( TOP VIEW ) Copyright © 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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