TMS418160A

1048576 BY 16-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997

15

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

Don’t

Care

Don’t Care

Valid

Out

Valid

Out

Valid

Out

RAS

UCAS

Address

W

DQ8 – DQ15

DQ0 – DQ7

OE

Column

Column

tRASP

tRCD

tCRP

tRP

tRSH

tPC

tCP

tASR

tRAH

tASC

tCAH

tCAL

tRAL

tRAD

tRCH

tRRH

tOHO

tOEZ

tRCS

tAA

tRAC

tAA

tOEA

LCAS

Row

Don’t Care

tCAC

Don’t

Care

tCPA

tCSH

tCAS

tCLZ

tRHCP

(see Note C)

tOH

See Note D

See Note D

tOHO

tOEA

tOFF

Don’t Care

Don’t Care

(see Note B)

tCLCH

(see Note A)

tCAS

NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.

B. tCAC is measured from xCAS to its corresponding DQx.

C. Access time is tCPA-, tAA-, or tCAC-dependent.

D. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.

E. A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write- and read-modify-write timing

specifications are not violated.

F. xCAS order is arbitrary.

Figure 7. Enhanced-Page-Mode Read-Cycle Timing