TMS418160A

1048576 BY 16-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997

14

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

RAS

xCAS

Address

W

OE

DQ0 – DQ15

tRWC

Row

Column

Don’t Care

Don’t Care

Don’t Care

Data

Out

Don’t Care

Don’t Care

Data

In

tRAS

tRCD

tT

tCAS

tRP

tCRP

tCP

tT

tCAH

tASC

tRAH

tASR

tRAD

tRCS

tRWD

tRWL

tWP

tAWD

tCWD

tCAC

tDS

tDH

tAA

tCLZ

tRAC

tOEA

tOEZ

tOEH

See Note A

tCWL

tOHO

tOED

NOTE A: Output can go from high-impedance state to an invalid-data state prior to the specified access time.

Figure 6. Read-Write-Cycle Timing