TMS418160A

1048576 BY 16-BIT

DYNAMIC RANDOM-ACCESS MEMORY

SMKS891C – AUGUST 1996 – REVISED OCTOBER 1997

11

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

(see Note B)

RAS

UCAS

LCAS

Address

W

DQ0 – DQ15

OE

Row

Column

tCAS

tRC

tRAS

tT

tRCD

tRP

tCP

tCRP

tRSH

tRAD

tRAH

tASC

tRAL

tCAH

tRRH

tCAC

tAA

tRAC

tOEA

tROH

tOEZ

Don’t Care

tRCS

tASR

Don’t Care

Don’t Care

tRCH

tOFF

Valid Data Out

tCLZ

tCLCH

(see Note A)

tOH

Don’t Care

Don’t Care

tOHO

tCSH

tCAL

See Note C

tCAS

NOTES: A. To hold the address latched by the first xCAS going low, the parameter tCLCH must be met.

B. tCAC is measured from xCAS to its corresponding DQx.

C. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.

D. xCAS order is arbitrary.

Figure 3. Read-Cycle Timing