RESET

VOUT2

VIN1

VIN2

EN

SEQ

VOUT1

VSENSE1

PG1

MR2

RESET

MR1

VSENSE2

VOUT2

VI

VOUT1

MR1

0.1

µF

10

µF

10

µF

0.1

µF

MR2

EN

TPS707xxPWP

(Fixed Output Option)

>2 V

<0.7 V

250 k

Ω

TPS70745, TPS70748, TPS70751, TPS70758, TPS70702

DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS

WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS

SLVS291 – MAY 2000

24

POST OFFICE BOX 655303

APPLICATION INFORMATION

sequencing timing diagrams (continued)

application conditions not shown in block diagram:

logic high; PG1 is tied to MR2; MR1 is left

unconnected and is therefore at logic high.

explanation of timing diagrams:

EN is initially high; therefore, both regulators are

off and PG1 and RESET are at logic low. With

reaches 95% of its regulated output voltage, PG1

regulated output voltages and both MR1 and MR2

(tied to PG1) are at logic high, RESET is pulled to

logic high after a 120 ms delay. When a fault on

output voltage, PG1 (tied to MR2) goes to logic

remains on because SEQ is high.

120 ms

EN

VOUT2

VOUT1

PG1

MR1

MR2

(MR2 tied to PG1)

RESET

SEQUENCE

95%

83%

83%

95%

NOTE A: t1 – Time at which both VOUT1 and VOUT2 are greater than the PG thresholds and MR1 is logic high.

t1

(see Note A)

Fault on VOUT1