OMAP3530 datasheet(5/239 Pages) TI

5 / 239 page

OMAP3525-HiRel and OMAP3530-HiRel Applications Processors

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SPRS599 – JUNE 2009

Table 1-1. Differences Between CBB and CBC Packages

FEATURE

CBB PACKAGE

CBC PACKAGE

For CBB package pin assignments

For CBC package pin assignments see

Pin Assignments

seeTable 2-1, Ball Characteristics (CBB

Table 2-2, Ball Characteristics (CBC Pkg.)

Pkg.)

Package-On-Package (POP) Interface

POP interface supported

Discrete Memory Interface

Discrete Memory Interface supported

Discrete Memory Interface not supported

Eight chip select pins available

GPMC

Four wait pins available

The following signals are either available on

CTS signal is available on 3 pins (triple

two (double muxed) or three pins (triple

muxed): uart1_cts (AG22 / W8 / T21),

UART1

muxed): uart1_cts (AE21 / T19 / W2),

uart1_rts (AH22 / AA9), uart1_tx (F28 / Y8 /

uart1_rts (AE22 / R2), uart1_rx (H3 / H25 /

AE7), uart1_rx (E26 / AA8)

AE4), uart1_tx (L4 / G26)

The following signals are available on two

pins (double muxed): uart2_cts (AF6/AB26),

pins (double muxed): uart2_cts (Y24/P3),

UART2

uart2_rts (AE6/AB25), uart2_tx (AF5/AA25),

uart2_rts (AA24/N3), uart2_tx (AD22/U3),

uart2_rx (AE5/AD25)

uart2_rx (AD21/W3)

The following signals are available on three

The following signals are available on two

pins (triple muxed): mcbsp3_dx (AF6 / AB26

pins (triple muxed): mcbsp3_dx (U17/ Y24/

McBSP3

/ V21), mcbsp3_dr (AE6 / AB25 / U21),

P3), mcbsp3_dr (T20/ AA24 / N3),

mcbsp3_clkx (AF5 / AA25 / W21), and

mcbsp3_clkx (T17/ AD22 / U3), mcbsp3_fsx

mcbsp3_fsx (AE5 / AD25 / K26)

(P20/ AD21 / W3)

The following signals are available on three

pins (triple muxed): gpt8_pwm_evt (N8 /

pins (triple muxed): gpt8_pwm_evt

GP Timer

AD25 / V3), gpt9_pwm_evt (T8 / AB26 / Y2),

(C5/AD21/V9), gpt9_pwm_evt (B4/W8/Y24),

gpt10_pwm_evt (R8 / AB25 / Y3), and

gpt10_pwm_evt(C4/U8/AA24),

gpt11_pwm_evt (P8 / AA25 / Y4)

gpt11_pwm_evt(B5/V8/AD22)

The following signals are available on two

pins (double muxed): mcbsp4_clkx (T8/AE1),

pins(double muxed): mcbsp4_clkx (B4 / V3),

McBSP4

mcbsp4_dr (R8/AD1), mcbsp4_dx (P8/AD2),

mcbsp4_dr (C4 / U4), mcbsp4_dx (B5 / R3),

mcbsp4_fsx (N8/AC1)

mcbsp4_fsx (C5 / T3)

HSUSB3_TLL

Supported

MM_FSUSB3

Supported

McSPI1

Four chip select pins are available

The following signals are available on two

MMC3

pins (double muxed): mmc3_cmd (AC3 /

pins (double muxed): mmc3_cmd (R8 / AB3),

AE10), and mmc3_clk (AB1 / AF10)

mmc3_clk (R9 / AB2)

GPIO

A maximum of 188 GPIO pins are supported. A maximum of 188 GPIO pins are supported.

DSI

Supported

SDI

Supported

This OMAP3525 and OMAP3530 Applications Processors data manual presents the electrical and

mechanical specifications for the OMAP3525 and OMAP3530 Applications Processors. The information

contained in this data manual applies to both the commercial and extended temperature versions of the

OMAP3525 and OMAP3530 Applications Processors unless otherwise indicated. It consists of the

following sections:

• A description of the OMAP3525 and OMAP3530 terminals: assignment, electrical characteristics,

multiplexing, and functional description (Section 2)

• A presentation of the electrical characteristics requirements: power domains, operating conditions,

power consumption, and dc characteristics (Section 3)

• The clock specifications: input and output clocks, DPLL and DLL (Section 4)

• The video DAC specification (Section 5)

• The timing requirements and switching characteristics (ac timings) of the interfaces (Section 6)

• A description of thermal characteristics, device nomenclature, and mechanical data about the available

packaging (Section 7)

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