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OMAP3530 Datasheet(PDF) 68 Page - Texas Instruments |
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OMAP3530 Datasheet(HTML) 68 Page - Texas Instruments |
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68 / 239 page  OMAP3525-HiRel and OMAP3530-HiRel Applications Processors SPRS599 – JUNE 2009 www.ti.com Table 2-5. External Memory Interfaces – GPMC Signals Description (continued) SIGNAL DESCRIPTION [2] TYPE BALL BALL BALL BOTTOM BALL TOP SUBSYSTEM NAME [1] [3] BOTTOM TOP (CBC Pkg.) [4] (CBC Pkg.) [5] PIN (CBB (CBB MULTIPLEXIN Pkg.) [4] Pkg.) [5] G [6] gpmc_d14 GPMC Data bit 14 IO W1 AB7 L2 J2 gpmc_a15/ gpmc_d14 gpmc_d15 GPMC Data bit 15 IO Y1 AC7 M2 K2 gpmc_a16/ gpmc_d15 gpmc_ncs0 GPMC Chip Select bit 0 O G4 Y2 AD8 AA8 - gpmc_ncs1 GPMC Chip Select bit 1 O H3 Y1 AD1 W1 - gpmc_ncs2 GPMC Chip Select bit 2 O V8 NA A3 - - gpmc_ncs3 GPMC Chip Select bit 3 O U8 NA B6 - - gpmc_ncs4 GPMC Chip Select bit 4 O T8 NA B4 - - gpmc_ncs5 GPMC Chip Select bit 5 O R8 NA C4 - - gpmc_ncs6 GPMC Chip Select bit 6 O P8 NA B5 - - gpmc_ncs7 GPMC Chip Select bit 7 O N8 NA C5 - - gpmc_io_dir GPMC IO direction control for O N8 NA C5 - - use with external transceivers gpmc_clk GPMC clock O T4 W2 N1 L1 - gpmc_nadv_al Address Valid or Address Latch O F3 W1 AD10 AA9 - e Enable gpmc_noe Output Enable O G2 V2 N2 L2 - gpmc_nwe Write Enable O F4 V1 M1 K1 - gpmc_nbe0_cl Lower Byte Enable. Also used for O G3 AC12 K2 - - e Command Latch Enable gpmc_nbe1 Upper Byte Enable O U3 NA J1 - - gpmc_nwp Flash Write Protect O H1 AB10 AC6 Y5 - gpmc_wait0 External indication of wait I M8 AB12 AC11 Y10 - gpmc_wait1 External indication of wait I L8 AC10 AC8 Y8 - gpmc_wait2 External indication of wait I K8 NA B3 - - gpmc_wait3 External indication of wait I J8 NA C6 - - Table 2-6. External Memory Interfaces – SDRC Signals Description SIGNAL DESCRIPTION TYPE(1) BALL BOTTOM BALL TOP BALL BOTTOM BALL TOP NAME (CBB Pkg.) (CBB Pkg.) (CBC Pkg.) (CBC Pkg.) sdrc_d0 SDRAM data bit 0 IO D6 J2 - D1 sdrc_d1 SDRAM data bit 1 IO C6 J1 - G1 sdrc_d2 SDRAM data bit 2 IO B6 G2 - G2 sdrc_d3 SDRAM data bit 3 IO C8 G1 - E1 sdrc_d4 SDRAM data bit 4 IO C9 F2 - D2 sdrc_d5 SDRAM data bit 5 IO A7 F1 - E2 sdrc_d6 SDRAM data bit 6 IO B9 D2 - B3 sdrc_d7 SDRAM data bit 7 IO A9 D1 - B4 sdrc_d8 SDRAM data bit 8 IO C14 B13 - A10 sdrc_d9 SDRAM data bit 9 IO B14 A13 - B11 sdrc_d10 SDRAM data bit 10 IO C15 B14 - A11 sdrc_d11 SDRAM data bit 11 IO B16 A14 - B12 sdrc_d12 SDRAM data bit 12 IO D17 B16 - A16 sdrc_d13 SDRAM data bit 13 IO C17 A16 - A17 (1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog). TERMINAL DESCRIPTION 68 Submit Documentation Feedback |
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