TMS320C6711FD167 datasheet(49/87 Pages) TI

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TMS320C6211, TMS320C6211B

FIXEDPOINT DIGITAL SIGNAL PROCESSORS

SPRS073L − AUGUST 1998 − REVISED JUNE 2005

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

ASYNCHRONOUS MEMORY TIMING

timing requirements for asynchronous memory cycles†‡§ (see Figure 18−Figure 19)

NO.

C6211−150

C6211−167

C6211B−150

C6211B−167

C6211BGFNA−150

UNIT

MIN

MAX

MIN

MAX

tsu(EDV-AREH)

Setup time, EDx valid before ARE high

th(AREH-EDV)

Hold time, EDx valid after ARE high

tsu(ARDY-EKOH)

Setup time, ARDY valid before ECLKOUT high

th(EKOH-ARDY)

Hold time, ARDY valid after ECLKOUT high

† To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in

the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide

enough (e.g., pulse width = 2E) to ensure setup and hold time is met.

‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are

programmed via the EMIF CE space control registers.

§ E = ECLKOUT period in ns

switching characteristics over recommended operating conditions for asynchronous memory

cycles for C6211 and C6211B‡§¶ (see Figure 18−Figure 19)

NO.

PARAMETER

C6211−150

C6211−167

C6211B−150

C6211B−167

UNIT

NO.

PARAMETER

MIN

MAX

MIN

MAX

UNIT

tosu(SELV-AREL)

Output setup time, select signals valid to ARE low

RS * E − 3

toh(AREH-SELIV)

Output hold time, ARE high to select signals invalid

RH * E − 3

td(EKOH-AREV)

Delay time, ECLKOUT high to ARE vaild

1.5

tosu(SELV-AWEL)

Output setup time, select signals valid to AWE low

WS * E − 3

toh(AWEH-SELIV)

Output hold time, AWE high to select signals invalid

WH * E − 3

td(EKOH-AWEV)

Delay time, ECLKOUT high to AWE vaild

1.5

1.2

‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are

programmed via the EMIF CE space control registers.

§ E = ECLKOUT period in ns

¶ Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0].

switching characteristics over recommended operating conditions for asynchronous memory

cycles for C6211BGFNA‡§¶ (see Figure 18−Figure 19)

NO.

PARAMETER

C6211BGFNA−150

UNIT

NO.

PARAMETER

MIN

MAX

UNIT

tosu(SELV-AREL)

Output setup time, select signals valid to ARE low

RS * E − 3

toh(AREH-SELIV)

Output hold time, ARE high to select signals invalid

RH * E − 3

td(EKOH-AREV)

Delay time, ECLKOUT high to ARE vaild

1.5

tosu(SELV-AWEL)

Output setup time, select signals valid to AWE low

WS * E − 3

toh(AWEH-SELIV)

Output hold time, AWE high to select signals invalid

WH * E − 3

td(EKOH-AWEV)

Delay time, ECLKOUT high to AWE vaild

‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are

programmed via the EMIF CE space control registers.

§ E = ECLKOUT period in ns

¶ Select signals include: CEx, BE[3:0], EA[21:2], AOE; and for writes, include ED[31:0].

TMS320C6711FD167 Datasheet(PDF) 49 Page - Texas Instruments

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