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TMS320C6711FD167 Datasheet(PDF) 22 Page - Texas Instruments |
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TMS320C6711FD167 Datasheet(HTML) 22 Page - Texas Instruments |
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22 / 87 page  TMS320C6211, TMS320C6211B FIXEDPOINT DIGITAL SIGNAL PROCESSORS SPRS073L − AUGUST 1998 − REVISED JUNE 2005 22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Terminal Functions SIGNAL TYPE† IPD/ IPU‡ DESCRIPTION NAME NO. TYPE† IPD/ IPU‡ DESCRIPTION CLOCK/PLL CLKIN A3 I IPD Clock Input CLKOUT1 D7 O IPD Clock output at device speed The CLK1EN bit in the EMIF GBLCTL register controls the CLKOUT1 pin. CLK1EN = 0: CLKOUT1 is disabled CLK1EN = 1: CLKOUT1 enabled to clock [default] CLKOUT2 Y12 O IPD Clock output at half of device speed When the CLKOUT2 pin is enabled, the CLK2EN bit in the EMIF global control register (GBLCTL) controls the CLKOUT2 pin. CLK2EN = 0: CLKOUT2 is disabled CLK2EN = 1: CLKOUT1 enabled to clock [default] CLKMODE0 C4 I IPU Clock mode select • Selects whether the CPU clock frequency = input clock frequency x4 or x1 PLLV§ A4 A¶ PLL analog VCC connection for the low-pass filter PLLG§ C6 A¶ PLL analog GND connection for the low-pass filter PLLF B5 A¶ PLL low-pass filter connection to external components and a bypass capacitor JTAG EMULATION TMS B7 I IPU JTAG test-port mode select TDO A8 O/Z IPU JTAG test-port data out TDI A7 I IPU JTAG test-port data in TCK A6 I IPU JTAG test-port clock TRST B6 I IPD JTAG test-port reset EMU5 B12 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected. EMU4 C11 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected. EMU3 B10 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected. EMU2 D10 I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected. EMU1 B9 I/O/Z IPU Emulation pin 1# EMU0 D9 I/O/Z IPU Emulation pin 0# RESETS AND INTERRUPTS RESET A13 I IPU Device reset NMI C13 I IPD Nonmaskable interrupt • Edge-driven (rising edge) Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin is not used, it is recommended that the NMI pin be grounded versus relying on the IPD. EXT_INT7 E3 External interrupts EXT_INT6 D2 I IPU External interrupts • Edge-driven EXT_INT5 C1 I IPU • Edge-driven • Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]) EXT_INT4 C2 Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]) HOST-PORT INTERFACE (HPI) HINT J20 O IPU Host interrupt (from DSP to host) HCNTL1 G19 I IPU Host control − selects between control, address, or data registers HCNTL0 G18 I IPU Host control − selects between control, address, or data registers HHWIL H20 I IPU Host half-word select − first or second half-word (not necessarily high or low order) HR/W G20 I IPU Host read or write select † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground ‡ IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite supply rail, a 1-k Ω resistor should be used.) |
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