PCF8579 datasheet(17/41 Pages) NXP

17 / 41 page

PCF8579_5

Product data sheet

Rev. 05 — 11 May 2009

17 of 41

NXP Semiconductors

PCF8579

LCD column driver for dot matrix graphic displays

8.7 Display RAM

The PCF8579 contains a 32

× 40-bit static RAM which stores the display data. The RAM

is divided into 4 banks of 40 bytes (4

× 8 × 40 bits). During RAM access, data is

transferred to or from the RAM via the I2C-bus.

8.7.1 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This

allows an individual data byte or a series of data bytes to be written into, or read from, the

display RAM, controlled by commands sent on the I2C-bus.

8.7.2 Subaddress counter

The storage and retrieval of display data is dependent on the content of the subaddress

counter. Storage and retrieval take place only when the contents of the subaddress

counter matches with the hardware subaddress at pins A0, A1, A2 and A3.

8.8 Command decoder

The command decoder identiﬁes command bytes that arrive on the I2C-bus.

The ﬁve commands available to the PCF8579 are deﬁned in Table 6.

The most-signiﬁcant bit of a command is the continuation bit C (see Table 7 and

Figure 14). Commands are transferred in WRITE mode only.

Table 6.

Deﬁnition of PCF8579 commands

Command

Operation code

Reference

Bit

set-mode

E[1:0]

M[1:0]

Table 8

set-start-bank

11111

B[1:0]

Table 9

device-select

A[3:0]

Table 10

RAM-access

G[1:0]

Y[1:0]

Table 11

load-X-address

X[5:0]

Table 12

Table 7.

C bit description

Bit

Symbol

Value

Description

continue bit

last control byte in the transfer; next byte will be regarded

as display data

control bytes continue; next byte will be a command too

C = 0; last command.

C = 1; commands continue.

Fig 14. General information of command byte

msa833

REST OF OPCODE

MSB

LSB

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