PCF8579 datasheet(15/41 Pages) NXP

15 / 41 page

PCF8579_5

Product data sheet

Rev. 05 — 11 May 2009

15 of 41

NXP Semiconductors

PCF8579

LCD column driver for dot matrix graphic displays

8.6.5 I2C-bus controller

The I2C-bus controller detects the I2C-bus protocol, slave address, commands and display

data bytes. It performs the conversion of the data input (serial-to-parallel) and the data

output (parallel-to-serial). The PCF8579 acts as an I2C-bus slave transmitter/receiver.

Device selection depends on the I2C-bus slave address, the hardware subaddress and

the commands transmitted.

8.6.6 Input ﬁlters

To enhance noise immunity in electrically adverse environments, RC low-pass ﬁlters are

provided on the SDA and SCL lines.

8.6.7 I2C-bus protocol

Two 7-bit slave addresses (0111100 and 0111101) are reserved for both the PCF8578

and PCF8579. The least signiﬁcant bit of the slave address is set by connecting input SA0

to either logic 0 (VSS) or logic 1 (VDD). Therefore, two types of PCF8578 or PCF8579 can

be distinguished on the same I2C-bus which allows:

1. One PCF8578 to operate with up to 32 PCF8579s on the same I2C-bus for very large

applications (see Table 16).

2. The use of two types of LCD multiplex schemes on the same I2C-bus.

In most applications the PCF8578 will have the same slave address as the PCF8579.

The I2C-bus protocol is shown in Figure 13. All communications are initiated with a START

condition (S) from the I2C-bus master, which is followed by the desired slave address and

read/write bit. All devices with this slave address acknowledge in parallel. All other devices

ignore the bus transfer.

In WRITE mode (indicated by setting the read/write bit LOW) one or more commands

follow the slave address acknowledgement. The commands are also acknowledged by all

addressed devices on the bus. The last command must clear the continuation bit C.

After the last command a series of data bytes may follow. The acknowledgement after

each byte is made only by the (A0, A1, A2 and A3) addressed PCF8579 or PCF8578 with

its implicit subaddress 0. After the last data byte has been acknowledged, the I2C-bus

master issues a STOP condition (P).

In READ mode, indicated by setting the read/write bit HIGH, data bytes may be read from

the RAM following the slave address acknowledgement. After this acknowledgement the

master transmitter becomes a master receiver and the PCF8579 becomes a slave

transmitter. The master receiver must acknowledge the reception of each byte in turn. The

master receiver must signal an end of data to the slave transmitter, by not generating an

acknowledge on the last byte clocked out of the slave. The slave transmitter then leaves

the data line HIGH, enabling the master to generate a STOP condition (P).

Display bytes are written into, or read from the RAM at the address speciﬁed by the data

pointer and subaddress counter. Both the data pointer and subaddress counter are

automatically incremented, enabling a stream of data to be transferred either to, or from

the intended devices.

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